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| digital controller for power supply applications with pmbus interface data sheet adp1055 rev. a document feedbac k information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2014C2015 analog devices, inc. all rights reserved. technical support www.analog.com features ?40c to +125c operation pmbus revision 1.2 compliant with pec and extended manufacturer specific commands 32-bit password protection with command masking 64 address selections (16 base addresses, expandable to 64) 6 pwm control signals, 625 ps resolution frequency from 48 khz to 1 mhz duty cycle double update rate digital control loop (pid + additional pole or zero configurability) programmable loop filters (ccm, dcm, low/normal temperature) fast line voltage feedforward adaptive dead time compensation for improved efficiency remote voltage sense redundant programmable ovp current sense primary side cycle-by-cycle fast protection secondary side cycle-by-cycle fast overcurrent protection secondary side averaged reverse current protection using diode emulation mode with fixed debounce synchronous rectifier control for improved efficiency in light load mode nonlinear gain for faster transient response from dcm to ccm frequency synchronization soft start and soft stop functionality average and peak constant current mode external pn junction temperature sensing 4 gpios (2 gpios configurable as active clamp snubber pwms) extended black box data recorder for fault recording user trimming on input and output voltages and currents digital current sharing applications isolated dc-to-dc power supplies and modules redundant power supply systems general description the adp1055 is a flexible, feature-rich digital secondary side controller that targets ac-to-dc and isolated dc-to-dc secondary side applications. the adp1055 is optimized for minimal component count, maximum flexibility, and minimum design time. features include differential remote voltage sense, primary and secondary side current sense, pulse-width modulation (pwm) generation, frequency synchronization, redundant ovp, and current sharing. the control loop digital filter and compensation terms are integrated and can be programmed over the pmbus? interface. programmable protection features include overcurrent (ocp), overvoltage (ovp) limiting, undervoltage lockout (uvlo), and external overtemperature (otp). the built-in eeprom provides extensive programming of the integrated loop filter, pwm signal timing, inrush current, and soft start timing and sequencing. reliability is improved through a built-in checksum and programmable protection circuits. a comprehensive gui is provided for easy design of loop filter characteristics and programming of the safety features. the industry-standard pmbus provides access to the many monitoring and system test functions. the adp1055 is available in a 32-lead lfcsp and operates from a single 3.3 v supply. typical application diagram figure 1. res add jtd gpio1 to gpio4 sda scl vdd agnd dgnd outa outb outc outd cs1 sr1 sr2 vff ishare v out sync nc vcore driver i coupler ? driver vs+ dc input load ovp cs2? cs2+ vs? jrtn v dd 12004-001 adp1055 ctrl smbalrt pmbus
adp1055 data sheet rev. a | page 2 of 140 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical application diagram .......................................................... 1 revision history ............................................................................... 3 functional block diagram .............................................................. 4 specifications ..................................................................................... 5 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 soldering ...................................................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 13 controller architecture ................................................................. 16 start-up and power-down sequencing ...................................... 17 vdd and vcore pins .............................................................. 17 power-up and power-down commands ............................... 17 power sequencing ...................................................................... 17 power-up and soft start routine ............................................. 17 soft stop routine ........................................................................ 17 vdd/vcore ovlo ................................................................ 18 control loop and pwm operation............................................. 19 voltage sense, feedback, and control loop ............................. 19 output voltage sense ................................................................. 19 digital filter ................................................................................ 19 digital filter programming registers ...................................... 20 digital compensation filters during soft start ..................... 20 filter transition .......................................................................... 20 pwm and synchronous rectifier outputs (outa, outb, outc, outd, sr1, sr2) ......................................................... 21 synchronous rectification ........................................................ 21 modulation limit ....................................................................... 22 switching frequency programming ........................................ 22 adcs and telemetry ...................................................................... 23 adcs for current sensing ........................................................ 23 adcs for voltage sensing ......................................................... 24 adcs for temperature sensing ................................................ 24 theory of operation ...................................................................... 25 accurate primary overcurrent protection ............................... 25 primary fast overcurrent protection ...................................... 25 matched cycle-by-cycle current limit (ocp equalization) ... 25 low temperature filter ............................................................. 25 voltage loop autocorrection ................................................... 25 nonlinear gain/response ......................................................... 26 integrator windup and output voltage regulation loss (overshoot protection) ............................................................. 26 accurate secondary overcurrent protection ......................... 26 secondary fast overcurrent protection .................................. 27 secondary fast reverse current protection ............................... 27 feedforward and input voltage sense ..................................... 27 accurate overvoltage and undervoltage protection ............. 28 fast overvoltage protection ...................................................... 28 external frequency synchronization ...................................... 28 temperature sensing ................................................................. 29 gpio and pgood signals ....................................................... 29 gpio3 and gpio4 as snubber pwm outputs ...................... 31 average constant current mode ............................................. 32 32-bit key code ......................................................................... 32 sr phase-in, sr transition, and sr fast phase-in ................ 33 output voltage slew rate .......................................................... 33 adaptive dead time compensation ....................................... 33 sr delay ....................................................................................... 34 current sharing (ishare pin) ................................................ 34 droop sharing ............................................................................ 36 light load mode and deep light load mode ....................... 37 pulse skipping ............................................................................. 37 soft stop ....................................................................................... 37 duty cycle double update rate .............................................. 37 duty balance, volt-second balance, and flux balancing ..... 38 fault responses and state machine mechanics ......................... 39 priority of faults ......................................................................... 39 flags ............................................................................................. 39 first fault id (ffid) ................................................................. 39 fault condition during soft start and soft stop ................... 40 watchdog timer ......................................................................... 40 standard pmbus flags ............................................................... 42 black box feature ........................................................................... 43 black box operation .................................................................. 43 black box contents .................................................................... 43 black box timing ....................................................................... 44 data sheet adp1055 rev. a | page 3 of 140 black box readback .................................................................... 45 black box power sequencing ..................................................... 45 power supply calibration and trim ............................................. 46 voltage calibration and trim .................................................... 46 cs1 trim ...................................................................................... 46 vff calibration and trim ......................................................... 46 pmbus digital communication .................................................... 47 features ......................................................................................... 47 overview ...................................................................................... 47 transfer protocol ......................................................................... 47 data transfer commands .......................................................... 48 group command protocol ........................................................ 49 clock generation and stretching .............................................. 49 start and stop conditions .......................................................... 49 repeated start condition ........................................................... 49 general call support .................................................................. 49 alert response address (ara) ................................................. 49 pmbus address selection .......................................................... 50 fast mode ..................................................................................... 50 10-bit addressing ........................................................................ 50 packet error checking................................................................ 50 electrical specifications .............................................................. 50 fault conditions .......................................................................... 50 timeout conditions ................................................................... 51 data transmission faults ........................................................... 51 data content faults .................................................................... 52 layout guidelines............................................................................ 53 cs2+ and cs2? pins ................................................................... 53 vs+ and vs? pins ....................................................................... 53 vdd pin ....................................................................................... 53 sda and scl pins ...................................................................... 53 cs1 pin ......................................................................................... 53 exposed pad................................................................................. 53 vcore pin .................................................................................. 53 res pin ......................................................................................... 53 jtd and jrtn pins ..................................................................... 53 ovp pin ....................................................................................... 53 sync pin ..................................................................................... 53 agnd and dgnd ..................................................................... 53 eeprom .......................................................................................... 54 overview ...................................................................................... 54 page erase operation ................................................................. 54 read operation (byte read and block read) ......................... 54 write operation (byte write and block write) ...................... 55 eeprom password .................................................................... 55 downloading eeprom settings to internal registers ......... 56 saving register settings to the eeprom ................................ 56 eeprom crc checksum ......................................................... 56 software gui ................................................................................... 57 standard pmbus commands supported by the adp1055 ....... 58 manufacturer specific commands ............................................... 60 standard pmbus command descriptions .................................. 62 standard pmbus commands .................................................... 62 manufacturer specific pmbus command descriptions ........... 86 supported switching frequencies ............................................... 126 outline dimensions ...................................................................... 140 ordering guide ......................................................................... 140 revision history 3/15rev. 0 to rev. a changes to table 1 ............................................................................ 7 changes to snubber configuration section ................................ 31 change to debounce bit, table 159 .............................................. 93 changes to supported switching frequencies section ............126 3/14revision 0: initial version adp1055 data sheet rev. a | page 4 of 140 functional block diagram figure 2. functional block diagram (simplified internal structure) vs? vs+ outc outd outa outb sr1 sr2 cs1 cs2? cs2+ ovp sync ishare vcore adc adc vff adc cs2 ocp2 irev vfb ovp cs1 ocp1 vff adc pwm engine dac 8kb eeprom digital compensator metering digital core i 2 c interface + ? 12004-002 adp1055 state machine adc gpio1 to gpio4 ldo uvlo vdd sda scl add jtd jrtn agnd ctrl res dgnd adc ref smbalrt data sheet adp1055 rev. a | page 5 of 140 specifications v dd = 3.0 v to 3.6 v, t a = ?40c to +125c, unless otherwise noted. fsr = full-scale range. table 1. parameter symbol test conditions/comments min typ max unit supply supply voltage v dd 4.7 f capacitor connected to agnd 3.0 3.3 3.6 v supply current i dd normal operation (ctrl pin is high) 63 ma normal operation (ctrl pin is low) 55 ma during eeprom programming (40 ms) i dd + 8 ma during black box write i dd + 8 ma current with vdd < vcore por 100 a power-on reset power-on reset por v dd rising 3.0 v undervoltage lockout uvlo v dd falling 2.75 2.85 2.97 v overvoltage lockout ovlo 3.8 4.0 4.1 v ovlo debounce set to 2 s (register 0xfe4d[5] = 0) 2.0 s set to 500 s (register 0xfe4d[5] = 1) 500 s vcore pin 0.33 f capacitor connected to dgnd power-on reset (por) v dd falling 2.1 v output voltage t a = 25c 2.6 v maximum time from por to outputs switching no black box recording (register 0xfe48[1:0] = 00) 10 ms with black box recording (register 0xfe48[1:0] = 01, 10, or 11) 45 ms oscillator and pll pll frequency res = 10 k (0.1%) 190 200 210 mhz outa, outb, outc, outd, sr1, sr2 pins output low voltage v ol sink current = 10 ma 0.8 v output high voltage v oh source current = 10 ma v dd ? 0.8 v rise time c load = 50 pf 3.5 ns fall time c load = 50 pf 1.5 ns voltage feedforward (vff pin) adc clock frequency 1.56 mhz feedforward (slow) input voltage range v ff for reporting; equivalent resolution of 12 bits 0 1 1.6 v adc usable input voltage range 0 1.57 v measurement accuracy (slow and fast feedforward) factory trimmed at 1.0 v 0% to 100% of usable input voltage range ?2.5 +2.5 % fsr 10% to 90% of usable input voltage range ?2.0 +2.0 % fsr 900 mv to 1.1 v ?1.5 +1.5 % fsr leakage current 1.0 a feedforward function (vff pin) feedforward (fast) input voltage range 0.6 1 1.6 v sampling period for feedforward (fast) adc equivalent resolution of 12 bits 1 s vs low speed adc input voltage range differential voltage from vs+ to vs? 0 1 1.6 v usable input voltage range 0 1.55 v adc clock frequency 1.56 mhz adp1055 data sheet rev. a | page 6 of 140 parameter symbol test conditions/comments min typ max unit adc update rate registers are updated at this rate, equivalent resolution of 12 bits 10.5 ms measurement accuracy factory trimmed at 1.0 v 0% to 100% of usable input voltage range ?2.75 +2.75 % fsr 10% to 90% of usable input voltage range ?2.0 +2.0 % fsr 900 mv to 1.1 v ?1.75 +1.75 % fsr temperature coefficient v dd = 3.3 v, vs = 1.0 v 110 ppm/c leakage current 1.0 a common-mode voltage offset error maximum voltage differential from vs? to agnd of 200 mv ?0.25 +0.25 % fsr vs ovp digital comparator vs ovp accuracy ?2.0 +2.0 % fsr vs ovp comparator speed register 0xfe4d[3:2] = 00, equivalent resolution of 7 bits 82 s vs uvp digital comparator vs uvp accuracy ?2.0 +2.0 % fsr propagation delay does not include debounce time (register 0xfe30[13:11] = 00) 80 s vs high speed adc sampling frequency 10 mhz equivalent resolution 6 bits dynamic range 50 mv fast ovp comparator (ovp pin) threshold accuracy factory trimmed at 1.206 v ?1.2 0 +1.5 % other thresholds (0.8 v to 1.6 v) ?2.0 +2.0 % propagation delay (latency) register 0xfe2f[1:0] = 00 40 80 ns current sense 1 (cs1 pin) input voltage range v in 0 1 1.6 v usable input voltage range 0 1.56 v adc clock frequency 1.56 mhz update rate registers are updated at this rate, equivalent resolution of 12 bits 10.5 ms current sense measurement accuracy factory trimmed at 1.0 v; tested under dc input conditions 10% to 60% of usable input voltage range ?1.5 +1.5 % fsr 10% to 90% of usable input voltage range ?2.0 +2.0 % fsr 0% to 100% of usable input voltage range ?2.5 +2.5 % fsr current sense measurement 12 bits cs1 fast ocp threshold register 0xfe2c[2] = 0 1.17 1.2 1.23 v register 0xfe2c[2] = 1 242 250 258 mv cs1 fast ocp speed 40 80 ns cs1 accurate ocp speed 10.5 ms leakage current 1.5 a current sense 2 (cs2+, cs2? pins) current sense measurement resolution for updating registers (constant current mode enabled or disabled) 12 bits adc clock frequency 1.56 mhz 30 mv range 1 register 0xfe4f[1:0] = 00 0 30 mv usable input range 0 21 mv 60 mv range 1 register 0xfe4f[1:0] = 01 0 60 mv usable input range 0 45 mv 480 mv range 1 register 0xfe4f[1] = 10 0 480 mv usable input range 0 414 mv data sheet adp1055 rev. a | page 7 of 140 parameter symbol test conditions/comments min typ max unit temperature coefficient v dd = 3.3 v 30 mv range 0 mv to 19 mv 326 ppm/c 0 mv to 21 mv 354 ppm/c 60 mv range 0 mv to 41 mv 172 ppm/c 0 mv to 45 mv 194 ppm/c 480 mv range 0 mv to 374 mv 83 ppm/c 0 mv to 414 mv 84 ppm/c current sense measurement accuracy (cs2+, cs2? pins) 30 mv setting 0 mv to 19 mv ?2.9 +2.9 % fsr 0 mv to 21 mv ?3.1 +3.1 % fsr 60 mv setting 0 mv to 41 mv ?1.9 +1.9 % fsr 0 mv to 45 mv ?2.1 +2.1 % fsr 480 mv setting 0 mv to 374 mv ?1.5 +1.5 % fsr 0 mv to 414 mv ?1.7 +1.7 % fsr internal level shifting current all ranges 25 a cs2 accurate ocp speed 2.6 ms common-mode voltage offset error (cs2+, cs2? pins) maximum voltage differential from cs2? to agnd of 50 mv 30 mv range ?1.0 +1.0 % fsr 60 mv range ?0.5 +0.5 % fsr 480 mv range ?0.25 +0.25 % fsr cs2 ocp fast comparators (cs2+, cs2? pins) for cs2 fast ocp and peak constant current mode cs2 forward comparator accuracy range of 0 mv to 60 mv threshold set at 0 mv ?10.3 % fsr threshold set at 15.24 mv ?10.1 % fsr threshold set at 30.48 mv ?23.8 +16.7 % fsr threshold set at 45.71 mv ?10.2 % fsr threshold set at 60 mv ?10.2 % fsr range of 0 mv to 600 mv threshold set at 0 mv ?0.8 % fsr threshold set at 152.4 mv 0.1 % fsr threshold set at 304.8 mv ?7.1 +7.6 % fsr threshold set at 457.1 mv 0.9 % fsr threshold set at 600 mv 1.3 % fsr reverse comparator accuracy range of 0 mv to 30 mv threshold set at 0 mv ?11.8 % fsr threshold set at 7.62 mv ?11.8 % fsr threshold set at 15.24 mv ?13.8 +16.9 % fsr threshold set at 22.86 mv 12.7 % fsr threshold set at 30 mv 12.5 % fsr range of ?30 mv to 0 mv threshold set at 0 mv 17.1 % fsr threshold set at ?7.62 mv 16.9 % fsr threshold set at ?15.24 mv ?9.5 +23.2 % fsr threshold set at ?22.86 mv 17.6 % fsr threshold set at ?30 mv 17.4 % fsr propagation delay register 0xfe2d[1:0] = 00 (diode emulation mode) 40 80 ns jtd temperature sense adc clock frequency 1.56 mhz update rate for updating registers (14-bit resolution) reverse sensing enabled 200 ms reverse sensing disabled 130 ms adp1055 data sheet rev. a | page 8 of 140 parameter symbol test conditions/comments min typ max unit measurement accuracy for external temperature sensor with bc847a transistor (n f = 1.00); register 0xfe5a[2:0] = 0x04 forward temperature sensor error fr om ?40c to +25c ?11.7 +13.4 c error from 25c to 125c ?8.9 +14.7 c reverse temperature sensor error from 25c to 125c ?9.7 +14.4 c ctrl, smbalrt , sync, gpio1 to gpio4, ishare pins digital inputs/outputs input low voltage v il 0.8 v input high voltage v ih v dd ? 0.8 v propagation delay 40 ns gpiox rise time gpiox configured as an output 3.5 ns gpiox fall time gpiox configured as an output 1.5 ns leakage current smbalrt , sync, gpio1 to gpio4, and ishare pins 1.0 a c trl pin 10.0 a sync pin synchronization to external frequency 50 1000 khz minimum on pulse 40 ns synchronization range 2 ?10.0 +10.0 % f sw leakage current 1.0 a black box programming time 1.2 36 1.2 ms sda/scl pins input low voltage v il 0.8 v input high voltage v ih 2.1 v output low voltage v ol 0.4 v leakage current 1.0 a serial bus timing see figure 3 clock operating frequency 10 100 400 khz bus free time t buf between stop and start conditions 1.3 s start hold time t hd;sta hold time after (repeated) start condition; after this period, the first clock is generated 0.6 s start setup time t su;sta repeated start condition setup time 0.6 s stop setup time t su;sto 0.6 s sda setup time t su;dat 100 ns sda hold time t hd;dat for write and for readback 300 ns scl low timeout t timeout 25 35 ms scl low period t low 1.3 s scl high period t high 0.6 s clock low extend time t lo;sext 25 ms scl, sda fall time t f 20 300 ns scl, sda rise time t r 20 300 ns eeprom reliability endurance 3 t j = 85c 10,000 cycles t j = 125c 1000 cycles data retention 4 t j = 85c 20 years t j = 125c 15 years 1 differential voltage from cs2+ to cs2?. 2 f sw is the switching frequenc y set in register 0x33. 3 endurance is qualified as per jedec st andard 22, method a117, and is measured at ?40c, + 25c, +85c, and +125c. 4 retention lifetime equivalent at junction temperature (t j ) = 85c as per jedec standard 22, method a117. retention lifetime derates with junction temperature. data sheet adp1055 rev. a | page 9 of 140 figure 3. serial bus timing diagram scl sda ps t buf t hd;sta t hd;dat t high t su;dat t hd;sta t su;sta t su;sto t low t r t f sp 12004-003 adp1055 data sheet rev. a | page 10 of 140 absolute maximum ratings table 2. parameter rating supply voltage (continuous), vdd 4.2 v digital pins: outa, outb, outc, outd, sr1, sr2, gpio1, gpio2, gpio3, gpio4, smbalrt , sync ?0.3 v to vdd + 0.3 v vs?, agnd, dgnd ?0.3 v to +0.3 v vs+ ?0.3 v to vdd + 0.3 v jtd, jrtn, add ?0.3 v to vdd + 0.3 v cs1, cs2+, cs2? ?0.3 v to vdd + 0.3 v sda, scl ?0.3 v to vdd + 0.3 v ishare ?0.3 v to vdd + 0.3 v operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c peak solder reflow temperature snpb assemblies (10 sec to 30 sec) 240c rohs-compliant assemblies (20 sec to 40 sec) 260c esd charged device model 500 v human body model 2.5 kv stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja jc unit 32-lead lfcsp 44.4 6.4 c/w soldering it is important to follow the correct guidelines when laying out the pcb footprint for the adp1055 and when soldering the device onto the pcb. for detailed information about these guidelines, see the an-772 application note . esd caution data sheet adp1055 rev. a | page 11 of 140 pin configuration and fu nction descriptions figure 4. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 ovp overvoltage protection. this signal is referenced to agnd and is used for redundant ovp protection. the nominal voltage at this pin should be 1 v. if this pin is not used, connect it to agnd. 2 vs+ noninverting voltage sense input. this signal is referenced to vs?. the nominal input voltage at this pin is 1 v. the resistor divider on this input must have a tolerance specific ation of 0.5% or better to allow for trimming. this pin is the input to the high frequency flash adc. 3 vs? inverting voltage sense input. there should be a low ohmic connection to agnd. the resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. to reduce common-mode noise, connect a 0.1 f capacitor from vs? to agnd. 4 cs2+ noninverting differential current sense input. this signal is referenced to cs2?. if this pin is not used, connect it to agnd. 5 cs2? inverting differential current sense input. if this pin is not used, connect it to agnd. this pin must have a low ohmic connection to agnd thought the sense resistor. 6 nc no connect. leave this pin unconnected. 7 vff voltage feedforward. two optional functions can be imple mented using this pin: feedforward and input voltage loss detection. this pin is typically connected upstream of the output inductor through a resistor divider network in an isolated converter. the nominal voltage at this pin shou ld be 1 v. this signal is referenced to agnd. if this pin is not used, connect it to agnd. 8 cs1 primary side current sense input. this pin is connected to the primary side current sensing adc and to the fast ocp comparator. this signal is referenced to pgnd. the re sistors on this input must have a tolerance specification of 0.5% or better to allow for trimming. if this pin is not used, connect it to agnd. 9 sr1 synchronous rectifier output. this pwm output connects to the input of a fet driver. this pin can be disabled when not in use. this signal is referenced to agnd. 10 sr2 synchronous rectifier output. this pwm output connects to the input of a fet driver. this pin can be disabled when not in use. this signal is referenced to agnd. 11 outa pwm output for primary side switch. this pin can be disa bled when not in use. this signal is referenced to agnd. 12 outb pwm output for primary side switch. this pin can be disa bled when not in use. this signal is referenced to agnd. 13 outc pwm output for primary side switch. this pin can be disa bled when not in use. this signal is referenced to agnd. 14 outd pwm output for primary side switch. this pin can be disa bled when not in use. this signal is referenced to agnd. 15 sync synchronization input signal. this pin is used as a refe rence for the internal pwm frequency. this signal is referenced to agnd and must have a nominal duty cycle of 50%. if this pin is not used, connect it to agnd and program register 0xfe55[6] = 1. 16 gpio4 programmable general-purpose input/output. if this pin is not used, connect it to agnd. this pin can also be configured as an active snubber pwm output. 17 gpio3 programmable general-purpose input/output. if this pin is not used, connect it to agnd. this pin can also be configured as an active snubber pwm output. notes 1. nc = no connect. leave this pin unconnected. 2. for increased reliabili t y of the solder joints and maximum therm a l capability, it is recommended that the exposed pad on the underside of the package be soldered to the pcb agnd plane. 24 ishare 23 smbalrt 22 sda 21 scl 20 ctrl 19 gpio1 18 gpio2 17 gpio3 1 2 3 4 5 6 7 8 ovp vs+ vs? cs2+ cs2? nc vff cs1 9 10 11 12 13 14 15 16 sr1 sr2 outa outb outc outd sync gpio4 32 31 30 29 28 27 26 25 jtd add res jrtn agnd dgnd vdd vcore adp1055 top view (not to scale) 12004-004 adp1055 data sheet rev. a | page 12 of 140 pin no. mnemonic description 18 gpio2 programmable general-purpose input/output. if this pin is not used, connect it to agnd. 19 gpio1 programmable general-purpose input/output. if this pin is not used, connect it to agnd. 20 ctrl power supply on input. this signal is referenced to agnd . this pin is the hardware pson control signal. it is recommended that a 1 nf capacitor be connected from the ctrl pin to agnd for decoupling. if this pin is not used, connect it to agnd. 21 scl i 2 c/pmbus serial clock input and output (open dr ain). this signal is referenced to agnd. 22 sda i 2 c/pmbus serial data input and output (open dr ain). this signal is referenced to agnd. 23 smbalrt power-good output (open drain). this signal is referenced to agnd. this pin is also used as the pmbus alert signal. 24 ishare digital current sharing input and output ( open drain). this signal is referenced to agnd. 25 vcore vdd for the digital core. connect a decoupling capacitor of at least 330 nf (1 f maximum) from this pin to dgnd as close to the ic as possible to minimize the pcb trace leng th. do not use the vcore pin as a reference or load it in any way. 26 vdd positive supply input. this signal is referenced to agnd . connect a 4.7 f decoupling capacitor from this pin to agnd as close to the ic as possible to minimize the pcb trace length. 27 dgnd digital ground. this pin is the ground reference for the digital circuitry. star connect to agnd. 28 agnd ic analog ground. 29 jrtn temperature sensor return. if this pin is not used, connect it to agnd. 30 res resistor input. this pin sets the internal reference for th e internal pll frequency. connect a 10 k resistor (0.1%) from res to agnd. do not load this pin with any capacitance. this signal is referenced to agnd. 31 add i 2 c/pmbus address select input. connect a resistor from add to agnd. this signal is referenced to agnd. 32 jtd thermal sensor input. a pn junction se nsor is connected from this pin to the jrtn pin. if this pin is not used, connect it to jrtn. ep exposed pad. for increased reliability of the solder jo ints and maximum thermal capability, it is recommended that the exposed pad on the underside of the package be soldered to the pcb agnd plane. data sheet adp1055 rev. a | page 13 of 140 typical performance characteristics figure 5. vs adc accuracy vs. temperature (from 10% to 90% of fsr) figure 6. cs1 adc accuracy vs. temperature (from 10% to 90% of fsr) figure 7. vff adc accuracy vs. temperature (from 10% to 90% of fsr) figure 8. cs2 30 mv adc accuracy vs. temperature (from 10% to 90% of fsr) figure 9. cs2 60 mv adc accuracy vs. temperature (from 10% to 90% of fsr) figure 10. cs2 480 mv adc accuracy vs. temperature (from 10% to 90% of fsr) ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 ?50 0 50 100 150 vs adc accuracy (%fsr) temperature (c) min spec min mean max max spec 12004-100 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 ?50 0 50 100 150 cs1 adc accuracy (%fsr) temperature (c) min spec min mean max max spec 12004-101 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 ?50 0 50 100 150 temperature (c) min spec min mean max max spec 12004-104 vff adc accurac y (%fsr) ?50 0 50 100 150 temperature (c) min spec min mean max max spec 12004-102 ?4 ?3 ?2 ?1 0 1 2 3 4 cs2 30mv adc accuracy (%fsr) ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 ?50 0 50 100 150 cs2 60mv adc accuracy (%fsr) temperature (c) min spec min mean max max spec 12004-103 ?50 0 50 100 150 temperature (c) min spec min mean max max spec 12004-105 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 cs2 480mv adc accuracy (%fsr) adp1055 data sheet rev. a | page 14 of 140 figure 11. ovp fast comparator at 1.206 v vs. temperature figure 12. cs1 ocp fast comparator at 1.2 v vs. temperature figure 13. cs1 ocp fast comparat or at 250 mv vs. temperature figure 14. cs2 forward comparator accuracy, 0 mv to 60 mv range figure 15. cs2 forward comparator accuracy, 0 mv to 600 mv range figure 16. cs2 reverse comparator, 0 mv to ?30 mv range ?50 0 50 100 150 temperature (c) min mean max max spec min spec 12004-106 ovp fast compa r a tor a t 1.206v (v) 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 1.225 1.230 ?50 0 50 100 150 temperature (c) min mean max max spec min spec 12004-107 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 cs1 ocp fast compar a tor a t 1.2v (v) ?50 0 50 100 150 temperature (c) min mean max max spec min spec 12004-108 240 242 244 246 248 250 252 254 256 258 260 cs1 ocp fast compa r a tor a t 250mv (mv) 12004-109 ?30 ?20 ?10 0 10 20 30 40 50 60 70 0102030405060 actu a l threshold (mv) programmed threshold (mv) min spec max spec mean 12004-110 ?100 0 100 200 300 400 500 600 700 0 100 200 300 400 500 600 actual threshold (mv) programmed threshold (mv) min spec max spec mean 12004-111 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 ?30 ?25 ?20 ?15 ?10 ?5 0 min spec max spec mean actual threshold (mv) programmed threshold (mv) data sheet adp1055 rev. a | page 15 of 140 figure 17. cs2 reverse comparator, 0 mv to 30 mv range figure 18. forward temperature sensor error vs. temperature figure 19. reverse temperature sensor error vs. temperature 12004-112 ?10 ?5 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 actual threshold (mv) programmed threshold (mv) min spec max spec mean ?50 0 50 100 150 temperature (c) min spec max spec 12004-113 mean max min ?15 ?10 ?5 0 5 10 15 20 forward tempe r a ture sensor error (c) temperature (c) 12004-114 mean ?15 ?10 ?5 0 5 10 15 20 reverse temper a ture sensor error (c) 0 20406080100120140 max spec min max min spec adp1055 data sheet rev. a | page 16 of 140 controller architecture the adp1055 is an application specific digital controller based on finite state machine (fsm) architecture. the adp1055 supports a subset of the pmbus revision 1.2 standard and also has extended manufacturer specific commands to provide a feature rich digital power product. dedicated adcs and comparators constitute the analog front end of the controller, feeding information to the digital core. the information is processed and used to generate the programmable pwm signals and to take action for various features such as light load or overvoltage/overcurrent protection. the adp1055 has six pwm outputs: outa to outd for the primary side switches and sr1 and sr2 for the secondary side synchronous rectifiers. the adp1055 allows individual programming of the pwm outputs to form the timing of the power switches for any power topology, such as full bridge, full bridge phase shifted, current doubler, or active clamp. primary side information (current or voltage) is sensed and processed via the cs1 and vff pins, whereas secondary side information is obtained via the cs2, ishare, vs, and ovp pins. a dedicated temperature sensor uses the jtd and jrtn pins. the input voltage is measured using the vff pin and is used for line voltage feedforward. extensive fault protection schemes are provided, and the controller also has a black box to record the state of the device (all sensor information including voltages, currents, temperatures, and flags) upon shutdown. i 2 c/pmbus communication is facilitated by the sda, scl, and smbalrt pins. four gpio pins can be used as flag output signals or as an interrupt service routine (isr) to trigger a pmbus fault action. the ctrl pin is used as described in the pmbus specification. detailed descriptions of all adp1055 features are provided in the theory of operation section. data sheet adp1055 rev. a | page 17 of 140 start-up and power-down sequencing vdd and vcore pins the proper amount of decoupling capacitance must be placed between the vdd and agnd pins, as close as possible to the device to minimize the trace length. it is recommended that the vcore pin not be loaded in any way. power-up and power-down commands the pmbus commands operation (register 0x01) and on_off_config (register 0x02) control the power-up and power-down behavior of the adp1055 . figure 20. operation (register 0x01) and on_off_config (register 0x02) power sequencing power sequencing is controlled using register 0x60 through register 0x66. the delays for the turn-on command (register 0x60, ton_delay) and the turn-off command (register 0x64, toff_delay) can each be programmed from 0 ms to 1024 ms in steps of 1 ms. the soft start ramp-up time (register 0x61, ton_rise) and the ramp-down time (register 0x65, toff_fall) can be programmed from 0 ms to 100 ms in steps of 1 ms. all values are rounded to the nearest available value. if a value is programmed outside the allowed range, it is forced to the nearest legal value. power-up and soft start routine when vdd is applied to the device, a certain time elapses before the adp1055 can regulate the power supply. 1. when vdd is above uvlo and vcore reaches above vcore por through an internal regulator, the adp1055 downloads the user settings from page 1 of the eeprom into the internal registers. 2. after the eeprom download, the adp1055 determines its address, programmed by the add pin and the i 2 c slave base address (register 0xd0, slv_addr_select). 3. the adp1055 waits for an idle time, after which the device is ready for normal operation. if the black box must erase a page to precondition the eeprom for storing, the idle time is extended by ~35 ms (see the black box timing section). 4. if the adp1055 is programmed to power up at this time (operation is enabled), the soft start ramp begins. otherwise, the adp1055 waits for the operation command. the outputs start switching, depending on the configuration of the operation command (register 0x01) and the on_off_ config command (register 0x02). if the adp1055 is programmed to be always on (register 0x02[4] = 0), the device begins the soft start ramp. figure 21 shows the entire soft start process. figure 21. example of soft start and soft stop settings in the gui the soft start proceeds as follows. 1. upon power-up, the adp1055 waits for the programmed ton_delay (register 0x60) and ramps to the regulation voltage according to the time programmed in ton_rise (register 0x61). 2. the soft start begins to ramp up the internal digital reference. the total duration of the soft start ramp is programmable using the ton_rise command. the ton_max command specifies the maximum on time before which the output voltage must exceed the vout_uv_fault_limit (register 0x44). if the vout_uv_fault_limit is set to 0, the ton_max value is ignored. if the soft start from precharge function is enabled (register 0xfe51[0] = 1), the soft start ramp starts from the current value of the output voltage sensed on vs and, therefore, the soft start ramp time is reduced proportionally. soft stop routine the soft stop process occurs in a manner similar to the soft start process, using the toff_delay, toff_max, and toff_fall commands. these commands are the counterparts of the ton_delay, ton_max, and ton_rise commands used for soft start. for more information about soft stop, see the soft stop section. 12004-015 12004-016 adp1055 data sheet rev. a | page 18 of 140 vdd/vcore ovlo the adp1055 has built-in overvoltage protection (ovp) on its supply rails. when the vdd or vcore voltage rises above the ovlo threshold, the response can be programmed using register 0xfe4d. it is recommended that when a vdd/vcore ovp fault occurs, the response be set to download the eeprom before restarting the adp1055 . all features related to the ovlo functionsuch as debounce, fault ignore, and download eeprom upon receiving a fault conditionare programmable using register 0xfe4d[7:4]. vdd overvoltage is ignored when the device is downloading information from the eeprom, even if the overvoltage occurs during the initial power-up or due to the setting of register 0xfe4d[6]. vdd overvoltage is recognized as a fault only after the eeprom download is complete. the adp1055 has a 4 ms idle time after an eeprom download. if the vdd overvoltage occurs during the ramp-up of vdd and the adp1055 has not initiated the eeprom download, the device responds according to the default setting of bit 7 in register 0xfe4d, which is to ignore vdd ov. data sheet adp1055 rev. a | page 19 of 140 control loop and pwm operation voltage sense, feedback, and control loop the vs pins are used for the monitoring and protection of the remote load voltage. the differential vs input pins are the main feedback sense point for the power supply control loop. the vs sense point on the power rail requires an external resistor divider to bring the nominal common-mode signal to 1 v at the vs pins. this resistor divider is programmed into vout_scale_loop and vout_scale_monitor accordingly. the resistor divider is necessary because the input range is 0 v to 1.6 v. the divided-down signal is internally fed into a high frequency (hf) adc. the hf adc is also the high frequency feedback loop for the power supply. output voltage sense the output voltage is fed back to the vs pins, where it is com- pared with a reference set by a 12-bit dac (see figure 22). the difference is then fed into the flash adc; in this configuration, the flash adc does not see the fraction of the output voltage set by the resistor divider, but instead sees only the error voltage. the error voltage is then fed into the digital filter, which decides the duty cycle command for the next switching period. the number of samples taken by the flash adc can be configured in register 0xfe67[7:4] (see table 215). the recommended configuration of this register is automatically configured using the gui. figure 22. output voltage sense and feedback the output voltage is also sampled using a low frequency adc. the output voltage is fed to a low-pass filter that is used to set the output of a trim dac; the trim dac finely adjusts the output voltage as part of the autocorrection loop (see the voltage loop autocorrection section). digital filter the loop response of the power supply can be changed using the internal programmable digital filter. a type 3 filter architecture has been implemented. to tailor the loop response to the specific application, the low frequency gain, zero location, pole location, and high frequency gain can all be set individually (see the digital filter programming registers section). it is recommended that the analog devices, inc., software gui be used to program the filter. the software gui displays the filter response in bode plot format and can be used to calculate all stability criteria for the power supply. from the sensed voltage to the duty cycle, the transfer function of the filter in z-domain is as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? add_pz z a z b hfg c zlfg d h(z) 1 1 1 256 1 256 1 )1( 1 where: a = filter pole register value (in decimal). b = filter zero register value (in decimal). c = high frequency gain register value (in decimal). d = low frequency gain register value (in decimal). lfg = 5.968 m 10 6 / f sw . hfg = 3.73 m 10 5 / f sw . m = 1 when 48.8 khz f sw < 97.7 khz. m = 2 when 97.7 khz f sw < 195.3 khz. m = 4 when 195.3 khz f sw < 390.6 khz. m = 8 when 390.6 khz f sw . add_pz is an additional pole or additional zero that can be added to the compensator. the additional zero takes this form: 1 256 1 ? ?? z e the additional pole takes this form: ? ? ? ? ? ? ?? ? 1 256 1 1 z e where e is the value (in decimal) of the additional pole zero frequency gain register (register 0xfe60 and register 0xfe61). to transfer the z-domain value to the s-domain, plug the follow- ing bilinear transformation equation into the h(z) equation: sf sf z(s) sw sw ? ? ? 2 2 where f sw is the switching frequency. the digital filter introduces an extra phase delay element into the control loop. the digital filter circuit sends the duty cycle information to the pwm circuit at the beginning of each switch- ing cycle (unlike an analog controller, which makes decisions on the duty cycle information continuously). therefore, the extra phase delay for phase margin, , introduced by the filter block is = 360 (f c / f sw ) where: f c is the crossover frequency. f sw is the switching frequency. at one-tenth the switching frequency, the phase delay is 36. for double update rate, the phase delay is reduced to 18. the gui lpf trim dac lf adc hf adc 50mv + ? dac vs adc (12 bits) vout_ov_limit vout_uv_limit dpwm ref adp1055 v out 12004-017 vs+ vs? adp1055 data sheet rev. a | page 20 of 140 incorporates this phase delay into its calculations. note that the gui does not account for other delays such as gate driver and propagation delays. digital filter programming registers three sets of registers allow three different filters to be programmed. ? normal mode filter (used for ccm or heavy load and configured in register 0xfe01 to register 0xfe04) ? light load mode filter (configured in register 0xfe05 to register 0xfe08) ? soft start filter (configured in register 0xfe09 to register 0xfe0c) the software gui allows the user to program the light load mode filter in the same manner as the normal mode filter. it is recommended that the gui be used for this purpose. digital compensation filters during soft start the adp1055 has a dedicated soft start filter (ssf) that can be used to fine-tune and optimize the dynamic response during the output voltage ramp-up. during soft start, the adp1055 determines the load condition and after the voltage reaches 12.5% of the nominal output voltage value, it determines the current load condition and switches filters accordingly to the light load mode threshold (register 0xfe5f[3:1]). if the load current is below the light load mode threshold, the adp1055 switches to the light load mode filter (llf). if the load current is above the light load mode threshold, the normal mode filter is used until the end of the soft start ramp, even if the device subsequently enters light load mode based on a change to the load current. other configurations can be programmed to use different filters during soft start, as follows: ? force soft start filter (register 0xfe51[2]). this option forces the adp1055 to use the soft start filter. in some cases, this option allows better fine-tuning of the ramp-up voltage. ? disable light load mode during soft start (register 0xfe51[1]). this option prevents the use of the light load mode filter during soft start, even if the light load condition is met. the light load mode filter is available for use after the end of the soft start ramp. figure 23 shows the use of filters during soft start. figure 23. digital filters during soft start (low temperature filter not shown) as shown in figure 23, in zone 1, the adp1055 starts with the normal mode filter or the soft start filter. zone 2 begins when the voltage reaches 12.5% of the nominal output voltage value. at this point, the adp1055 checks whether the system is in light load mode, and the choice of filter is based on the following criteria: ? if the system is in light load mode, the adp1055 switches to the light load mode filter (unless the option to disable the llm filter was previously selected). ? if the system is not in light load mode, the adp1055 continues to use the filter used in zone 1: the normal mode filter or the soft start filter. the adp1055 changes to the llm filter if the load changes during zone 2 (voltage rises from 12.5% to 100% of the soft start ramp. the filter does not revert to llm if the load drops until after the end of soft start. in zone 3 the filter changes to the nmf or llm filter, depending on the load. filter transition to avoid output voltage glitches and to provide a seamless transition from one filter to another, the adp1055 supports programmable filter transitions. this feature allows a gradual transition from one filter to another. filter transitions are programmed using register 0xfe4a[2:0]. when the adp1055 switches filters, the switching action is changed in 32 steps. the step size can be programmed over several cycles (1t sw to 32t sw ) to avoid glitches in the output. the filter used depends on the state of the synchronous rectifiers and whether the system is in continuous conduction mode (ccm) or discontinuous conduction mode (dcm) (see table 5). table 5. state of synchronous rectifiers and filter used state of srx outputs load regular mode diode emulation mode filter used medium to heavy load srs in ccm srs in ccm normal mode filter (register 0x fe01 to register 0xfe04). below llm threshold srs in llm diode emulation srs llm filter (register 0xfe05 to register 0xfe08.) when diode emulation mode is in use, the llm filter is activated after the llm threshold is crossed. deep llm srs are off srs are off llm filter (register 0xfe05 to register 0xfe08). 12004-018 ps on 12.5% ref nmf/ssf zone 1 llf nmf/ssf llm/nmf based on load llm/nmf based on load nmf/ssf ramp time 0x5f v out zone 3 zone 2 data sheet adp1055 rev. a | page 21 of 140 pwm and synchronous rectifier outputs (outa, outb, outc, outd, sr1, sr2) the pwm and sr outputs are used for control of the primary side drivers and the synchronous rectifier drivers. these outputs can be used for several control topologies, such as full-bridge, phase-shifted zvs configurations and interleaved, two switch forward converter configurations. delays between the rising and falling edges can be individually programmed (see figure 24). figure 24. pwm timing diagram take special care to avoid shoot-through and cross-conduction. it is recommended that the software gui be used to program these outputs. figure 25 shows an example configuration to drive a full-bridge topology with synchronous rectification. figure 25. pwm pin assignment for fu ll-bridge, phase-sh ifted topology with synchronous rectification go and auto go command the pwm outputs (outa to outd) and the sr outputs (sr1 and sr2) are all synchronized with each other. therefore, when reprogramming more than one of these outputs, it is important to first update all the registers and then latch the information into the adp1055 at the same time. this simultaneous updating of the pwm outputs is facilitated by the go command (register 0xfe00). the go command acts as a gate to apply all functions related to the commands at the same time. the go command gates the following functions: ? frequency synchronization ? line voltage feedforward ? double update rate, volt-second balance ? digital filter settings ? frequency and pwm settings ? voltage reference change during reprogramming, the outputs are temporarily disabled. it is recommended that the pwm outputs be disabled when not in use. the pmbus allows the user to change the voltage setting and the switching frequency on-the-fly. the auto go command (register 0xfe5b) is an added level of protection that restricts the user from making a change to certain commands (see table 203). for more information about the various programmable switching frequencies and pwm timings, see the switching frequency programming section. synchronous rectification sr1 and sr2 are recommended for use as the pwm control signals when using synchronous rectification. these pwm signals can be configured much like the other pwm outputs. t 2 t 4 t 1 t 5 t 11 t 7 t 8 t 10 t period t period t 9 t 6 t 3 t 12 pwm1 (outa) pwm2 (outb) pwm3 (outc) pwm4 (outd) sync rect 1 (sr1) sync rect 2 (sr2) 12004-020 isolator driver driver outa outb outc outd sr1 sr2 v in outa outd outc outb sr1 sr2 12004-019 adp1055 data sheet rev. a | page 22 of 140 modulation limit the modulation limit register (register 0xfe53) can be programmed to apply a maximum duty cycle modulation limit to any pwm signal, thus acting as a clamp for the maximum modulation range of any pwm output. when modulation is enabled, the maximum modulation limit is applied to all pwm outputs collectively. as shown in figure 26, this limit is the maximum time variation for the modulated edges from the default timing, following the configured modulation direction. figure 26. modulation limit settings there is no minimum duty cycle limit setting. therefore, the user must set the rising edges and falling edges based on the case with the least modulation to enter pulse skipping mode under very light load conditions. each lsb in register 0xfe53[6:0] corresponds to a unit of a base time step size. the base time step size (20 ns, 40 ns, 80 ns, or 160 ns) depends on the switching frequency; therefore, the modulation limit is based on the value in register 0xfe53[6:0] multiplied by the corresponding base time step size. the modulated edges are prevented from extending beyond one switching cycle, but the maximum duty cycle is 100% (the minimum pulse width is 5 ns). the gui provided with the adp1055 is recommended for programming this feature (see figure 27). figure 27. setting modulation limits (modulation range shown by arrows) switching frequency programming the frequency_switch command (register 0x33) sets the switching frequency of the adp1055 in kilohertz. this command has two data bytes formatted in the linear data format; the programmable frequency ranges from 48 khz to 1000 khz. the adp1055 does not support every possible frequency due to the infinite combinations of exponent and mantissa values that can be programmed. if a programmed frequency does not exactly match a supported value, it is rounded up to the nearest available frequency. it is recommended that the read_frequency command (register 0x95) be used to determine the exact value of the switching frequency. table 244 lists the supported frequencies. outx t modulation_limit t rx t fx 12004-021 12004-022 data sheet adp1055 rev. a | page 23 of 140 adcs and telemetry two kinds of adcs are used in the adp1055 : ? low frequency (lf) - adcs that runs at 1.56 mhz for accurate measurement and telemetry ? high frequency (hf) flash adcs for the feedback and control loop - adcs have a resolution of one bit and operate differently from traditional flash adcs. the equivalent resolution obtain- able depends on how long the output bit stream of the - adc is sampled. - adcs also differ from nyquist rate adcs in that the quan- tization noise is not uniform across the frequency spectrum. at lower frequencies, the noise is lower, and at higher frequencies, the noise is higher (see figure 28). figure 28. noise performance for nyquist rate and - adcs the low frequency adc runs at approximately 1.56 mhz. for a specified bandwidth, the equivalent resolution can be calculated as follows: ln(1.56 mhz/ bw )/ln2 = n bits for example, at a bandwidth of 95 hz, the equivalent resolution/noise is ln(1.56 mhz/95)/ln2 = 14 bits at a bandwidth of 1.5 khz, the equivalent resolution/noise is ln(1.56 mhz/1.5 khz)/ln2 = 10 bits the adc output information is available in the value registers (register 0xfe96 to register 0xfea3) or through the pmbus read_x commands, where x = vout, iout, and so on. adcs for current sensing the adp1055 has two current sense inputs: cs1 and cs2. these inputs sense, protect, and control the primary input current and the secondary output current information. the cs1 and cs2 inputs can be calibrated to reduce errors due to external components for accurate telemetry. cs1 adc for primary side current the cs1 pin is typically used for the monitoring and protection of the primary side current. the primary side current is sensed using a current transformer (ct). the input signal at the cs1 pin is fed into the cs1 adc for current monitoring. figure 29 shows the typical configuration for the current sense. the read_iin command reports the average input current; this reading is updated every 10.5 ms. figure 29. current sense 1 (cs1) operation cs2 adc for secondary side current the cs2+ and cs2? pins are differential inputs used for the monitoring and protection of the secondary side current. the adp1055 supports differential sensing using low-side current sensing with two ranges for the adc: 30 mv and 60 mv. the low input range is used to operate in level shifting mode, when the cs2 terminals are connected directly to the shunt resistor (see figure 30). in this mode, a pair of internal resistors and current sources are used to perform the necessary level shifting. in this mode, only low-side current sensing is possible, and the adc range is programmable to 30 mv or 60 mv. figure 30. differential low-side sensing magnitude frequency nyquist adc noise - ? adc noise 12004-023 cs1 1k ? 10 ? i = 100ma i = 10a v in outa outb outc outd adc 12 bits vref fast ocp 1:100 1v 12004-027 cs2? agnd cs2 ranges range1 = 0mv to 30mv range2 = 0mv to 60mv cs2 fast ocp 0mv to 60mv/6 bits (step size 0.952mv) cs2 adc iout_oc_limit iout_uc_limit cs2 irev limit 0mv to ?30mv (step size 0.4762mv) i load adp1055 cs2+ 12004-025 adp1055 data sheet rev. a | page 24 of 140 an additional range of 480 mv (single-ended input only) can be used for high-side sensing or simply as an input with a higher range (see figure 31). the high input range is used for operation in single-ended mode, where external circuitry must be provided for level shifting of the current signal. figure 31. single-ended high-side sensing the read_iout command reports the average output current; this reading is updated every 2.6 ms. adcs for voltage sensing vff adc for input voltage the vff pin is typically used for the monitoring and protection of the primary side voltage. figure 32 shows a typical configuration for the feedforward circuit. figure 32. feedforward configuration the input voltage signal can be sensed at the secondary winding of the isolation transformer before the output inductor and must be filtered by an rcd network to eliminate the voltage spike at the switch node (see figure 32). in nonisolated topologies, the vff adc is connected directly to the primary voltage via a resistive divider with some filtering to eliminate voltage spikes on the bulk capacitor when the power switch is turned on or off. the read_vin command reports the average input voltage; this reading is updated every 10.5 ms. vs adc for output voltage the vs pins of the adp1055 are used for the monitoring, control, and protection of the power supply output. typically, the output voltage is divided down using a resistive divider such that at the rated output, there is 1.0 v on the vs pins. the read_vout command reports the average output voltage; this reading is updated every 10.5 ms. adcs for temperature sensing for information about the temperature sensing adcs, see the temperature sensing section. cs2? cs2+ agnd cs2+ range: 0mv to 480mv cs2 fast ocp 0mv to 600mv/7 bits (step size 9.52mv) cs2 adc iout_oc_limit iout_uc_limit cs2 irev limit 0mv to ?30mv (step size 0.4762mv) i load r sns v out adp1055 12004-024 digital filter 1/x dpwm engine vff adc 0v to 1.6v 0.6v to 1.6v vff feedforward adc r r1 r2 vx from secondary winding 12004-026 data sheet adp1055 rev. a | page 25 of 140 theory of operation accurate primary overcurrent protection the cs1 adc is used to measure the average value of the primary current. the 12 msbs of the reading (cs1_value, register 0xfe98[13:4]) are converted into pmbus format and compared to the threshold set using the pmbus command iin_oc_fault_limit (register 0x5b) to make a fault decision. the fault response is set by the iin_oc_fault_ response command (register 0x5c). primary fast overcurrent protection the input signal on the cs1 pin is also fed into a comparator for pulse-by-pulse ocp protection. the fast ocp comparator is used to limit the peak primar y current within each switching cycle. two thresholdsthe 250 mv or 1.2 v thresholdare programmable using register 0xfe2c[2]. when the cs1 ocp threshold is crossed, the pwm outputs (outa to outd) are immediately terminated for the remainder of the switching cycle. for the full-bridge topology, where the switching period is divided into two halves, a cs1 ocp event during one half does not terminate the pwm outputs for the second half. the cs1 ocp comparator provides programmable blanking and debounce to prevent false triggering; these features are programmable using register 0xfe4e and register 0xfe2c. the comparator also features a programmable timeout condition (set in register 0xfe4e[2:0]), which specifies that the cs1 fast ocp condition must be present for a specified number of consecutive switching cycles before the iin_oc_fast_fault flag is set. the cs1 fast ocp fault can also be set using the gpio1 general-purpose input/output pin. matched cycle-by-cycle current limit (ocp equalization) for a half-bridge converter, the cycle-by-cycle limit feature cannot guarantee an equal duty cycle between the two half cycles of the switching period. the imbalances of each half cycle can cause the center point voltage of the capacitive divider to drift from v in /2 (half the input voltage) toward either ground or the input voltage. this drift, in turn, can lead to output voltage regulation failure, transformer saturation, and the doubling of voltage stress on the synchronous rectifiers. to avoid these problems, the adp1055 implements a matched cycle-by-cycle limit. this feature produces a pwm pulse width in the second half cycle that is of equal duration as the preceding pulse when a cs1 fast ocp event occurs (iin_oc_fast_ fault). in other words, when a cycle-by-cycle limit is triggered, the adp1055 forces the duty cycle in the subsequent half cycle to be exactly the same as that of the previous half cycle. however, if the cs1 cycle-by-cycle current limit always has the highest priority to terminate the pwm outputs meaning that if a cycle-by-cycle fault occurs during the period where the duty cycle is being equalized, the cycle-by-cycle current fault takes priority. the cs1 ocp duty cycle equalization feature (register 0xfe57[6]) can be enabled for all topology configurations. the edge selection is the same as for the volt-second balance feature. low temperature filter during the soft start process, the soft start filter can be used in combination with the normal mode filter and the light load mode filter. the soft start filter can be configured as a low temperature filter. using register 0xfe62[1:0], the low temperature filter is activated on one of three selectable inputs: the external forward temperature reading, the external reverse temperature reading, or the rising edge of gpio2. the low temperature pole is activated at a temperature of 10c; subsequent thresholds are at 6c, 2c, and so on, down to ?14c (register 0xfe62[6:4]). the temperature hysteresis is programmed in steps of 5c in register 0xfe62[3:2]. the change of filters from one to another always takes place after a 2 sec time hysteresis plus any other filter transition speed. it is recommended that the adp1055 gui be used to program this feature. table 6 summarizes the use of the filters for low and high temperatures. table 6. filter options for low and high temperatures load condition low temperature high temperature light load light load filter light load filter heavy load with low temperature, filter disabled ssf/nmf with add_pz ssf/nmf with add_pz heavy load with low temperature, filter enabled ssf with add_pz ssf/nmf with add_pz voltage loop autocorrection output voltage sampling is performed using the high speed nyquist adc. the output voltage is sampled just before the end of the switching period (t sw ) or just before half the switching period (t sw /2) if double update rate is enabled. the output voltage ripple ramp changes as the input voltage changes, causing the sampling voltage to also change. assuming a steady state condition, any dc offsets can be eliminated by sampling the output voltage synchronously with the switching frequency. due to the relationship between the output voltage ripple ramp and the input voltage, the average output voltage can drift to a higher value when the input voltage is at its maximum value. to correct for this drift, the adp1055 uses a low frequency auto- correction loop based on the lf adc on the vs pins. under ideal conditions, the voltage on this input is 1.0 v. adp1055 data sheet rev. a | page 26 of 140 the lf adc is trimmed in production and has high accuracy over supply, voltage, and temperature; therefore, the autocorrection loop eliminates all errors due to offsets in the high frequency adc. the adp1055 assumes that the voltage on the lf adc is accurate and precise and changes the setpoint (or reference) accordingly so that the vs pins measure 1.0 v. any additional offset in the output voltage is due to the tolerances of the external resistor dividers alone. the speed of the autocorrection loop can be changed using register 0xfe4a[5:3]. this feature can also be disabled. the autocorrection loop stores the correction value until the adp1055 is power cycled. when the power is turned off and then on again, the autocorrection loop is repeated to maintain the most accurate output voltage. figure 33. output voltage sampling point at minimum and maximum input voltage nonlinear gain/response to enhance the dynamic performance of the power supply during a load transient, the nonlinear gain can be used. the error voltage is the reference voltage minus the divided-down output voltage by use of a resistive divider. during steady state, this error voltage is 0 v. during a transient condition, the error voltage is not zero and the digital compensator acts on the error voltage and adjusts the control input to correct for the error. this may take several switching cycles, especially during a transition from dcm to ccm. in such cases, a boosted error signal aids in reducing the settling time and can even avoid an overshoot in some cases. the adp1055 has a programmable increase in error voltage depending on how far the absolute error voltage is with respect to 0 v. there are four ranges: 1% to 2%, 2% to 3.5%, 3.5% to 4%, and >4%. the nonlinear gain boost is programmable in register 0xfe5e and register 0xfe29[0]. it is recommended that the loop gain of the power supply be measured with the highest programmed gain setting. it is also recommended that an additional gain margin of 4 db be used when this feature is used due to the nonlinear effect. figure 34. ideal settings for nonlinear gain (highest gain setting for highest error) integrator windup and output voltage regulation loss (overshoot protection) the adp1055 limits the amount of integrator gain when the output voltage is out of regulation for a long period of time due to any of the following: ? large reduction in input voltage ? large and sudden change in output voltage setpoint ? excessive load the adp1055 limits the amount of integrator gain to prevent overshoot caused by integrator windup. when duty cycle saturation occurs due to any of these conditions, there is an inherent lag in the system because the integrator is the slowest element of the feedback control path. the adp1055 inherently prevents the integrator gain from increasing beyond a large value, but offers an additional layer of protection. if the output voltage is out of regulation for more than a certain number of switching cycles, the reference/setpoint is set to the current output voltage, and a soft start from precharge is initiated at a rate programmed by the vout_transition_rate command (register 0x27). this behavior eliminates any overshoot in the output voltage. this setting and the number of switching cycles can be programmed in register 0xfe4a[7:6]. accurate secondary overcurrent protection the cs2 adc is used to measure the average value of the secondary current via the cs2 pins. the 12 msbs of the reading (cs2_value, register 0xfe99[13:2]) are converted into pmbus format and compared to the configured threshold to make a fault decision. the lsb of the reading is equal to cs2 range /2 x where: cs2 range is the value set in register 0xfe4f[1:0]. x is the number of bits in register 0xfe4b[4:3]. t sw v ripple v in_min v in_max time time 2 1 t sw 2 t sw 3 t sw 0v 0v sample here sample here sample here 12004-028 ?4 ?4 ?3 ?3 ?2 ?1 0 1 2 3 4 ?2 ?1 0 error voltage (%hf adc fsr) boosted gain 1234 0xfe29[0] = 0 0xfe29[0] = 1 12004-029 data sheet adp1055 rev. a | page 27 of 140 thresholds and limits can be set for cs2 using these pmbus commands: iout_oc_fault_limit (register 0x46) and iout_oc_warn_limit (register 0x4a). the fault response is programmable in register 0x47. secondary fast overcurrent protection the input signal on the cs2 pins is also fed into two comparators for fast ocp protection. the fast ocp comparator is used to limit the instantaneous secondary current in either the positive or the negative direction. the cs2 ocp comparator also features a programmable timeout condition (set in register 0xfe4f[6:4]), which specifies that the cs2 fast ocp condition must be present in consecutive switching cycles before the iout_oc_fast_fault flag is set. when the cs2 fast ocp comparator is used to sense the output inductor current instead of the load current (see figure 1), the comparator can be used for cycle-by-cycle peak current limiting of the inductor current. cycle-by-cycle peak current limiting is executed by the termination of the pwm outputs (outa to outd) to disable power transfer to the secondary side. in an isolated buck derived topology, the inductor current during the on time of the primary switch is a fraction of the inductor current; this feature can be used when the cs1 pin is not used. the cs2 fast ocp threshold can be set in steps of 9.52 mv for the 480 mv cs2 adc range and in steps of 0.952 mv for the 30 mv and 60 mv cs2 adc ranges using register 0xfe2d. secondary fast reverse current protection a programmable comparator is used to detect reverse current. the comparator can also be used for diode emulation mode to improve light load efficiency. the iout_uc_fast fault is set when the cs2 reverse comparator is asserted. after it is set, the iout_uc_fast fault is cleared between 328 s and 656 s after the deassertion of the cs2 reverse comparator. for all three cs2 adc ranges (30 mv, 60 mv, and 480 mv), the threshold is programmed in register 0xfe2e[7:2], and the debounce is programmed in register 0xfe2e[1:0]. the operation of diode emulation mode depends on the accurate sensing of the zero crossing of the inductor current, which in turn is dependent on proper sensing of the inductor current through the sense resistor. the accuracy of the fast reverse current protection is heavily dependent on the sensing of the inductor current; proper layout techniques (kelvin sensing) must be followed. the fast reverse current comparator range is extended to a positive range (0 mv to 30 mv) in addition to the negative range (?30 mv to 0 mv). with this dual range, an accurate sensing of the zero crossing can be tweaked and trimmed to turn off the synchronous rectifiers at exactly the zero crossing of the inductor current by compensating for the gate driver delay and layout inadequacies and by ensuring that there is no excessive voltage stress or voltage spike across the devices. feedforward and input voltage sense the adp1055 supports voltage line feedforward control to improve line transient performance. the feedforward scheme modifies the modulation value based on the vff voltage. when the vff input is 1 v, the line feed- forward has no effect. for example, if the digital filter output remains unchanged and the vff voltage changes to 50% of its original value (but still higher than 0.5 v), the modulation of the falling edges of outa to outd doubles (see figure 35). the voltage line feedforward function is optional and is program- mable using register 0xfe29 and register 0xfecd[2:0]. it is recommended that feedforward be enabled during soft start. the vff voltage must be set to 1 v when the nominal input voltage is applied. the voltage at the vff pin is sampled synchro- nously with the switching period and, therefore, the decision to modify the pwm outputs based on input voltage is performed at this rate. typically, the feedforward block can detect and respond to a 3% change in input voltage and make a change to the pwm outputs approximately every 1 s. to prevent false triggering of the feedforward block due to noise/voltage spikes on the vff pin that are carried from the switch node, a small filter capacitor may be needed. the filter capacitor should not be too large, and the time constant should typically be much less than 1 s. an additional adc connected to the vff pin is used to report the adc value and therefore, the input value, using the resistive dividers. the primary input voltage can be calculated by multiplying vx by the turns ratio (n1/n2), as follows: v primary = vx ( r1 + r2 )/ r2 ( n1/ n2) for fault comparison, the input voltage is monitored using the vff adc, and the 9 msbs (vff_value, register 0xfe96[13:2]) are converted into pmbus format and compared to the threshold to make a fault decision. fault limits and their responses can be set using pmbus commands such as vin_uv_fault_limit (register 0x59), vin_ov_fault_limit (register 0x55), vin_uv_fault_response (register 0x5a), and vin_ov_fault_response (register 0x56). figure 35. feedforward control on modulation v ff digital filter o utput outx t modulation t s t s t modulation 12004-031 adp1055 data sheet rev. a | page 28 of 140 accurate overvoltage and undervoltage protection accurate overvoltage protection is provided by the pmbus commands vout_ov_fault_limit (register 0x40), vout_ov_fault_response (register 0x41), and vout_ov_warn_limit (register 0x42). similarly, accurate undervoltage protection is provided by the pmbus commands vout_uv_warn_limit (register 0x43), vout_uv_fault_limit (register 0x44), and vout_uv_ fault_response (register 0x45). all readings are obtained from the low frequency - adc on the vs+ and vs? pins. the accurate ovp fault decision is taken after a sampling interval of 82 s (7-bit averaged value). for ovp, additional sampling time up to a maximum of 320 s can be programmed in steps of 82 s using register 0xfe4d[3:2]. if additional sampling time is enabled, the ov fault condition must be present for the number of additional samples programmed before the vout_ov flag is set. the nominal output voltage at the vs pins is 1 v, and the ovp and uvp thresholds are set above and below this level. for uvp, the output voltage is monitored using the low frequency - adc; the nine msbs of the reading (vs_value, register 0xfe97[13:5]) are converted into pmbus format and compared with the output undervoltage fault limit threshold. ovp functions similarly, but uses the seven msbs of the reading (register 0xfe97[13:7]). fast overvoltage protection the adp1055 has a dedicated ovp pin for redundant overvoltage protection. this pin performs fast overvoltage protection, where a comparator compares the fractional output voltage by means of resistive dividers to the voltage set by a dac (see figure 36). the nominal output voltage at the ovp pin is 1 v. the ovp threshold is programmable using register 0xfe2f[7:2]. a debounce time (from 40 ns to 10 s) can be added using register 0xfe2f[1:0] before the fault response is taken. the fault response is set using the manufacturer specific command vout_ov_fast_fault (register 0xfe34). figure 36. fast overvoltage protection external frequency synchronization the adp1055 has a sync pin that is used for frequency synchronization. the internal digital phase-locked loop (dpll) is capable of determining the master frequency on the sync pin (f sync ) and locking the internal switching frequency to the external frequency. the lock or capture range is 10% of the switching frequency, which is programmed using the frequency_ switch command (register 0x33). the pwm outputs are synchronized to the outa pin at the start of the switching period. for example, consider a duty cycle on outa where the rising (or falling) edge of outa is at a time of x s after the t = 0 of the switching period. after synchronization, the time difference between the rising edge of the external master synchronization frequency (f sync ) and the rising (or falling) edge of outa is x s. the other pwm outputs are adjusted accordingly. in short, frequency synchronization also locks on to the phase. the dpll can recognize the external master frequency within one clock cycle and, after the dpll has locked on to f sync , the time required to achieve synchronization depends on how far apart f sync and the internal switching frequency (f sw ) are. a typical synchronization time when f sync jumps from 90 khz to 110 khz with f sw = 100 khz is approximately 200 s. the synchronization time depends on the bandwidth of the dpll, which is approximately f sw /25. therefore, a higher f sw translates to a higher bandwidth. using the interleave command (register 0x37), a phase shift in steps of 22.5 can be added. additional functions that are part of the standard pmbus interleave command include the group id number and the respective number in the group, both programmable using register 0x37. the adp1055 supports only a specific number of switching frequencies. due to the pwm programming resolution of 5 ns for programming the minimum and maximum pwm modulation limit, the switching frequency and the master clock frequency may not be an exact multiple of each other. although the dpll can detect f sync exactly, due to the quantization of the internal frequency settings, there is a possibility that f sync and f sw may not be the same and may differ by a small amount. to prevent the frequency from jumping from one value of f sw to another (which causes the switching period to change) due to the quantization of f sw , f sw is set to the closest quantized value to f sync rounded down. due to this effect or due to a non-ideality (jitter) of the master clock, a dither can be added to the clock frequency (using register 0xfe55[1]) of 5 ns or 10 ns. using this dither, f sw is equal to f sync on average. for a full-bridge topology, it is recommended that register 0xfe55[0] = 0 so that half the switching period is an exact multiple of 5 ns. 6-bit threshold fast ovp 0.8v to 1.6v step size = 12.5mv dac agnd ovp adp1055 v out 12004-032 data sheet adp1055 rev. a | page 29 of 140 after synchronization, if the master clock suddenly changes to 0 hz, the adp1055 continues to operate at the last known master frequency. however, if the device is power cycled through a soft start, the master frequency is not retained, and the adp1055 defaults to the internal frequency set by frequency_switch (register 0x33). if the device is off and the master frequency is already present on the sync pin, the switching frequency is already set to the master frequency when the adp1055 turns on. it is recommended that the synchronization function be disabled when not in use (register 0xfe55[6] = 1) because switching noise may be coupled into the sync pin. the switching frequency can be read back using the pmbus command read_frequency (register 0x95). figure 37. tracking of sync function temperature sensing the adp1055 has two external temperature sensors. for the external temperature sensors, pn junction devices such as transistors are connected back to back; these devices are called forward diode and reverse diode (see figure 38). figure 38. temperature sensor, forward and reverse sensing the temperature can be read using the following standard pmbus commands: read_temperature_2 (register 0x8e) for the external sensing forward diod e, and read_temperature_3 (register 0x8f) for the external sensing reverse diode. the adp1055 measures the temperature readings of the external forward diode and the external reverse diode in that order. using proprietary zero offset circuitry (patent pending), the inputs to the adcs are zeroed out before each temperature measurement to compensate for temperature dependent offset variation, which affects the measurement result. this allows the forward and reverse sensing pn diodes to be kept far away from each other without affecting the reading significantly due to offset errors. the adp1055 is factory calibrated at ambient temperature for minimum error using the bc847a transistor (with n f = 1.00) placed in the position of forward diode. the nonideality factor (n f ) of the transistor in v be = n f v t ln(i/i s ). care must be taken to isolate the thermal sensor so that switching noise is not coupled into the base by the parasitic capacitances from base to ground and emitter to ground. it is recommended that a low-pass filter be added by placing a large capacitor of 220 pf to 470 pf across the base emitter junction to remove any noise. adding a reverse diode introduces an additional error due to the reverse leakage current. the reference current (i ref ), used for the sensing algorithm to 10 a, can be programmed by setting register 0xfe5a[2:0] = 0x04. the update rate for each subsequent temperature reading (external forward reading, followed by external reverse reading) is approximately 200 ms if reverse sensing is enabled, and approximately 130 ms if reverse sensing is disabled, with 14-bit resolution (register 0xfe5a[6:5] = 0x3). overtemperature protection (otp) can be set using ot_fault_limit (register 0x4f), ot_fault_response (register 0x50), and ot_warn_limit (register 0x51). otp functions for the forward diode only. the hysteresis for otp is the difference between the ot_fault_limit and ot_warn_ limit values. for example, if ot_fault_limit is set to disable all pwm outputs at 125c and ot_warn_limit is set to 115c, the adp1055 stops switching at 125c and begins switching again only when the temperature falls below 115c. gpio and pgood signals four dedicated pins serve as general-purpose inputs/outputs (gpios). each pin can be configured as an input or output with a programmable polarity (set in register 0xfe40). do not change the configuration of the pin from input to output or from output to input on the fly. figure 39. gpio1 configured as an output with normal polarity figure 40. gpio1 configured as an input with negated polarity when the pin is configured as an input, a programmable action can be taken (similar to the pmbus voltage faults) using register 0xfe39 to register 0xfe3c (gpiox_fault_response). when the gpiox pin is configured as an output, internal signals known as pgood1 and pgood2 can be logically combined and output on the pin. the logic functions for the gpio pins are programmable in register 0xfe41 and register 0xfe42. 12004-033 master clock frequency ( f sync ) synchronization time depends on dpll bandwidth synchronization time depends on dpll bandwidth frequenc y nominal f sw time internal switching frequency ( f sw ) unit on unit on unit off 110% f sw 90% f sw jtd forward diode reverse diode jrtn 12004-034 12004-035 12004-036 adp1055 data sheet rev. a | page 30 of 140 figure 41. logical functions available using pgood1 (logic) pgood2 various flags can be programmed into pgood1 and pgood2 using register 0xfe44 and register 0xfe45. when coupled with the gpios, these flags can be used to trigger signals to provide external logic functions by means of discrete circuits. for example, in figure 42, the overtemperature flag or the vin_uv flag can set pgood2. this feature is useful for signaling the power chain downstream so that any appropriate action can be taken. a delay (debounce) can be added to the pgoodx signals using register 0xfe43. figure 42. signals routed into pgood1 and pgood2 in addition to triggering the gpios, the pgood1_fault and pgood2_fault flags are set in register 0xfe93[6] (fault_unknown[6]) and register 0xfe93[7] (fault_ unknown[7]) (where 0 means no fault). the same debounce applies to the flags. the power_good_on register (register 0x5e) sets the voltage that the output voltage must exceed before power_good can be set. similarly, the output voltage must fall below the power_good_off threshold (set in register 0x5f) for power_good to be reset. figure 43. power_good flag tripped by vout note that the pmbus signal power_good cannot be brought out to the gpiox pins, but it can be brought out to the smbalrt pin. the pmbus signal power_good is accessible through status_word (register 0x79[11]). power_good is asserted (0 means power is good) only if all of the following conditions are met: ? vout has exceeded power_good_on. ? vout has not fallen below power_good_off. ? pgood1_fault is not set. ? pgood2_fault is not set. uvp is not associated with this flag; however, the pgood1_ fault and pgood2_fault flags can be programmed to select uvp (vout_uv_fault). there is no debounce for power_good . figure 44. power_good signal path 12004-037 12004-038 12004-039 v out nomin a l vout_uv power_good pson time power_good_on vout_uthd set and reset logic v out reset power_good_off vout_lthd set pgood1_fault power_good pgood2_fault off 12004-040 data sheet adp1055 rev. a | page 31 of 140 gpio3 and gpio4 as snubber pwm outputs the gpio3 and gpio4 pins of the adp1055 can be configured as two signals used for an active snubber. this circuitry can be used to provide a drive signals for an active clamp. snubber configuration the on time of the snubber and the dead time of the snubber signals can be programmed using register 0xfe63 and register 0xfe64[5:0], respectively. the active clamp signals turn on after a selectable dead time (0 ns to 315 ns in steps of 5 ns, programmable using register 0xfe64[5:0]). using register 0xfe65[7], the active clamp signals can be configured on one of the following: ? falling edge of sr1 or sr2 signal ? falling edge of outc and outd the snubber signal stays on for a fixed value regardless of the duty cycle and load condition programmed in register 0xfe63. however, the snubber signal is toggled as soon as it encounters the next srx rising edge or the next outx falling edge, even if the programmed on time is of a greater value. figure 45. active clamp snubber configured on srx signals figure 46. active clamp snubber configured on outx signals miscellaneous snubb er configuration using register 0xfe64[7:6]), the snubber configuration can be set to one of these options: ? option 1: both gpio3 and gpio4 are configured as regular signals, as described in the gpio and pgood signals section (see figure 47). ? option 2: gpio3 is configured as an active snubber pwm output; gpio4 is configured as a regular signal (see figure 48). ? option 3: gpio3 is configured as a regular signal; gpio4 is configured as an active snubber pwm output (see figure 49). ? option 4: both gpio3 and gpio4 are configured as active snubber pwm outputs (see figure 50). figure 47. option 1: gpio3 and gpio4 configured as regular signals figure 48. option 2: gpio3 configured as an active snubber pwm output; gpio4 configured as a regular signal figure 49. option 3: gpio3 configured as a regular signal; gpio4 configured as an active snubber pwm output figure 50. option 4: gpio3 and gpio4 configured as active snubber pwm outputs the gpio polarity bit can be configured using the same bits described in the gpio and pgood signals section. the polarity bit allows true versatility with the use of either p channel or n channel fets, depending on the application. these pwm signals can be blanked during soft start and soft stop using register 0xfe46[14] and register 0xfe47[14]. the signals are active as long as the system does not shut down in response to a fault condition or a psoff command is issued. 12004-041 12004-042 12004-043 12004-044 12004-045 12004-046 adp1055 data sheet rev. a | page 32 of 140 average constant current mode the adp1055 supports constant current (cc) mode. the constant current mode threshold is set in one of two ways: ? using the pmbus definition of cc mode (register 0xfe4f[2] = 0) ? using the manufacturer specific cc mode (register 0xfe4f[2] = 1) in both modes, the constant current limit can be set as a percentage of the iout_oc_fault_limitfor example, 3.125%, 6.25%, 12.5%, 25%, 50%, or 100%using register 0xfe5d[3:0]. in the pmbus definition of cc mode, the constant current mode is activated on a iout_oc_fault fault, and the load current is limited to the cc limit, as specified in register 0xfe5d[3:0]. only positive percentages are applicable when the pmbus definition of cc mode is used. the fault responses to iout_oc_fault in this case are defined as per the pmbus format. the system enters cc mode on detection of the cs2 current (~2.6 ms, 12-bit averaging of cs2 adc). any further changes in the current while the device is in cc mode take place according to the averaging speed selectable in register 0xfe4f[7]. for cc mode to work properly using the pmbus faults, the iout_oc_fault debounce must be set to 0 ms. in the manufacturer specific cc mode, the cc limit is exactly the limit that is programmed, and there is no need to trip the iout_oc_fault before entering cc mode. fault responses to iout_oc_fault in this case are to ignore the fault or to shut down the device in response to the fault (register 0x47[7:6] = 11). other settings programmed in the response section (for example, register 0x47[7:6] = 00, 01, or 10) are ignored. below the iout_oc_fault_limit threshold, the adp1055 operates in constant voltage mode, using the output voltage as the feedback signal for closed-loop operation. when the adp1055 crosses the constant current mode threshold, the cs2 current reading is used to control the output voltage regulation point. the output voltage is ramped down linearly as the load increases to ensure that the load current remains constant. figure 51. typical characteristics in constant current (cc) mode the constant current control loop has relatively low bandwidth because the current is averaged over a 328 s period (9-bit decimation of the cs2 bit stream). the output voltage changes at a maximum rate of 1.18 v/sec at the vs pins; therefore, the instantaneous value of the current can exceed the constant current limit for a very short period of time, depending on the severity of the transient condition. for a faster dynamic response of the constant current mode, the turbo mode can be used. in turbo mode, the averaging time can be decreased to a period of ~41 s (6-bit decimation of the cs2 bit stream). in turbo mode, the slew rate of the output voltage can be programmed using register 0xfe5d[5:4]. as the output voltage is reduced to maintain a constant load current, xxx_fault_response (for example, register 0x47[7:6] = 01) can be used to program a fault response when the output voltage falls below a specific threshold set by iout_oc_lv_limit (register 0x48). it is important to note that although constant current mode can be applied to any current fault (input or output current) according to the pmbus specification, the adp1055 applies the constant current mode only to maintain a constant output current. for example, if the iout_uc_fault is programmed to enter constant current mode, the adp1055 does not boost the output voltage to maintain the current level set by iout_uc_limit. using the manufacturer specific fault response for constant current mode, the system can be forced into constant current mode at a specific threshold, and if this threshold persists for a specified amount of time (based on the debounce time), the iout_oc_fault is tripped (see figure 52). figure 52. constant current with hiccup 32-bit key code the adp1055 supports a 32-bit password (key code) in addition to the eeprom password set by register 0xd5. this 32-bit key code enables another level of protection for the user and the manufacturer to limit access to certain commands and operations. v out iout (0,0) iout_oc_fault_limit 12004-047 12004-048 vout nominal iout_oc_fast cc limit i out_oc_fault_limit time iout nominal iout_oc_ debounce starts iout_oc_ debounce starts converter starts after ret ry attempt iout_oc_debounce ends and fault trips hiccup iout_oc_ debounce starts dependent on slew rate and cc turbo mode data sheet adp1055 rev. a | page 33 of 140 entering the key code the key code is a unique 32-bit pass code that is entered using the key_code command (register 0xd7). because this com- mand is a block read/block write command, the first data byte of this command is the number of bytes (4). when entering the key code, the data has this format: {0x04, keycode[7:0], keycode[15:8], keycode[23:16], keycode[31:17]}. (note the low byte to high byte order of the 32-bit key code.) after the correct key code is entered, the user has full write access to all commands, including pmbus and manufacturer specific com- mands such as cmd_mask (register 0xf4) and extcmd_ mask (register 0xf5), which ca n be used to disable other commands using the command masking feature. the key code is also needed to change the eeprom password (register 0xd5). command mask the command mask feature allows any pmbus command or manufacturer specific command to be masked in the adp1055 . if the command is masked, a read or a write to that command results in a no acknowledge (nack). pmbus commands are masked using register 0xf4; manufacturer specific commands are masked using register 0xf5. using command masking, the user can block access to certain commandssuch as commands that configure the switching frequency, the digital compensator, or the output voltage setpointwhile allowing access to the readback commands (read_x, where x = iout, in, vout, vin, and so on). the slv_ad dr_select (register 0xd0), eeprom_password (register 0xd5), key_code (register 0xd7), eeprom_info (register 0xf1), cmd_mask (register 0xf4), and extc md_mask (register 0xf5) commands are not maskable. it is recommended that the adp1055 gui be used to configure the masking function (see figure 53). figure 53. snapshot of the gui showing lock and unlock of commands changing the key code to change the key code, first unlock the eeprom as described in the unlock the eeprom section. 1. after the eeprom is unlocked, enter the 32-bit key code (default key code is 0xffffffff) using the key_code command (register 0xd7). 2. enter the new key code using the same command, for example, 0x1feedbac (a pneumonic for negative feedback in twos complement format). 3. the key code is now changed to the new key code. save the new key code into the user settings page of the eeprom using the store_user_all command (register 0x15). sr phase-in, sr transition, and sr fast phase-in the sr1 and sr2 outputs are recommended for use as the pwm control signals when using synchronous rectification for the output (or secondary) rectifiers. these pwm signals can be configured similar to other pwm outputs. figure 54. example of sr outp uts in light load mode (llm) figure 55. example of sr outputs in heavy load (ccm) when the mode changes from llm to ccm, an abrupt change in the sr outputs may cause the output voltage to dip momentarily. an optional sr transition process (during which the pulse width of the sr pwm outputs is increased slowly) can be applied to the sr1 and sr2 outputs. the sr transition can be enabled by setting register 0xfe50[5]. the speed at which the sr edges move from zero duty cycle to maximum duty cycle (as determined by the control loop) can be programmed from 5 ns per t sw to 5 ns per 1024 t sw (t sw = switching cycle) using register 0xfe5f[7:4]. output voltage slew rate the output voltage slew rate (or transition rate) can be set using the pmbus vout_transition_rate command (register 0x27). the slew rate determines how quickly the output voltage is adjusted in response to a change in the digital reference. the fastest slew rate supported by the adp1055 is 1 kv/sec, and the slowest rate is 14.3 v/sec. a pmbus command setting of 0 sets the slew rate to the slowest setting. this slew rate is the rate that the internal setpoint reference can change; the actual change of the output voltage depends on the bandwidth of the control loop and its ability to track the reference. the vout_transition_rate command can be disabled using register 0xfe65[2]. adaptive dead time compensation register 0xfe1d to register 0xfe24 are the adaptive dead time (adt) registers. these registers allow the dead time between 12004-049 12004-050 12004-051 adp1055 data sheet rev. a | page 34 of 140 pwm edges to be adapted on the fly. the adt feature is activated when the primary or secondary current (cs1 or cs2) falls below the threshold programmed in register 0xfe1e. the software gui allows the user to easily program the dead time values, and it is recommended that the gui be used for this purpose. figure 56. adaptive dead time window in the gui before adt is configured, the primary current threshold must be programmed. each individual pwm rising and falling edge (t 1 to t 12 ) can then be programmed to have a specific dead time offset at no load (zero current). this offset can be positive or negative and is relative to the nominal edge position. when the current is between zero and the threshold, the amount of dead time is linearly adjusted in steps of 5 ns. the averaging period of the cs1/cs2 current is selected using register 0xfe1e[7], and the speed of the dead time adjustment can also be programmed to accommodate faster or slower adjustment in register 0xfe1d[5:0]. for example, if the cs1 threshold is set to 2 a, t 1 has a nominal rising edge of 100 ns. if the adt setting for t 1 is 40 ns at no load, t 1 moves to 140 ns when the current is 0 a and to 120 ns when the current is 1 a. similarly, adt can be applied in the negative direction. the adt feature is useful in quasi resonant topologies where an energy transfer occurs from the inductor (generally, from one or more of the leakage inductance, magnetizing inductance, and external inductance) to the capacitor (usually the drain-source capacitance of the mosfet power switch) for the purpose of achieving zero voltage switching (zvs). generally, the condition for ensuring zvs is that the energy in the inductor must exceed the energy in the capacitor. a resonant transition occurs when energy is dumped from the inductor to the capacitor (capacitor being charged with opposite polarity voltage). at one point, there is close to 0 v across the mosfet, and at this point the power switch is turned on. if this energy is not sufficient, the mosfet turns on without zvs. in this case, adt can be used to wait until the resonant transition reaches its peak value so that a near zvs turn-on is achieved. sr delay the adp1055 is well suited for dc-to-dc converters in isolated topologies. each time a pwm signal crosses the isolation barrier, an additional propagation delay is added due to the isolating com- ponents. the adp1055 allows programming of an adjustable delay (0 ns to 315 ns in steps of 5 ns) using register 0xfe52[5:0]. this delay moves both sr1 and sr2 later in time with respect to outa to outd to compensate for the added delay due to the isolating components. in this way, the edges of all pwm outputs can be aligned, and the sr delay can be applied separately as a constant dead time. current sharing (ishare pin) the adp1055 supports both analog current sharing and digital current sharing. the adp1055 can use either the cs1 current information or the cs2 current information for current sharing. analog current sharing analog current sharing uses the internal current sensing circuitry to provide a current reading to an external current error amplifier. therefore, an additional differential current amplifier is not necessary. the current reading from cs1 or cs2 can be output to the ishare pin in the form of a digital bit stream, which is the output of the current sense adc (see figure 57). the bit stream is proportional to the current delivered by this unit to the load. by filtering this digital bit stream using an external rc filter, the current infor- mation is turned into an analog voltage that is proportional to the current delivered by this unit to the load. this voltage can be compared to the share bus voltage. if the unit is not supplying enough current, an error signal can be applied to the vs feed- back point. this signal causes the unit to increase its output voltage and, in turn, its current contribution to the load. figure 57. analog current share configuration 12004-052 current sense adc share bus lpf bit stream bit stream ishare voltage current cs2? cs2+ 12004-054 data sheet adp1055 rev. a | page 35 of 140 digital share bus the digital share bus scheme is similar in principle to the tradi- tional analog share bus scheme. the difference is that instead of using a voltage on the share bus to represent current, a digital word is used. the adp1055 outputs a digital word onto the share bus. the digital word is a function of the current that the power supply is providing (the higher the current, the larger the digital word). the power supply with the highest current controls the bus (master). a power supply that is putting out less current (slave) sees that another supply is providing more power to the load than it is. during the next cycle, the slave increases its current output contri- bution by increasing its output voltage. this cycle continues until the slave outputs the same current as the master, within a programmable tolerance range. figure 58 shows the configu- ration of the digital share bus. figure 58. digital current share configuration the digital share bus is based on a single-wire communication bus principle; that is, the clock and data signals are contained together. when two or more adp1055 devices are connected, they syn- chronize their share bus timing. this synchronization is performed by the start bit at the beginning of a communications frame. if a new adp1055 is hot-swapped onto an existing digital share bus, the device waits to begin sharing until the next frame. the new adp1055 monitors the share bus until it sees a stop bit, which designates the end of a share frame. it then performs synchroni- zation with the other adp1055 devices during the next start bit. the digital share bus frame is shown in figure 60. figure 59 shows the possible signals on the share bus. figure 59. share bus high, low, and idle bits the length of a bit (t bit ) is fixed at 10 s. a logic 1 is defined as a high-to-low transition at the start of the bit and a low-to-high transition at 75% of t bit . a logic 0 is defined as a high-to-low transition at the start of the bit and a low-to-high transition at 25% of t bit . the bus is idle when it is high during the whole period of t bit . all other activity on the bus is illegal. glitches up to t glitch (200 ns) are ignored. the digital word that represents the current information is eight bits long. the adp1055 takes the eight msbs of the cs1 or cs2 reading (the current share signal specified in register 0xfe2b[3]) and uses this reading as the digital word. when read, the share bus value at any given time is equal to the cs1 or cs2 current reading (see figure 61). figure 60. digital current share frame timing diagram digital word share bus current sense info ishare power supply a digital word current sense info ishare power supply b v dd 12004-053 logic 1 logic 0 idle previous bit next bit t 1 t 0 t bit 12004-056 8-bit data previous frame start bit 0 2 stop bits (idle) start bit 0 2 stop bits (idle) next frame frame 12004-055 adp1055 data sheet rev. a | page 36 of 140 digital share bus scheme each power supply compares the digital word that it is outputting with the digital words of all the other supplies on the bus. round 1 in round 1, every supply first places its msb on the bus. if a supply senses that its msb is the same as the value on the bus, it continues to round 2. if a supply senses that its msb is less than the value on the bus, it means that this supply must be a slave. when a supply becomes a slave, it stops communicating on the share bus because it knows that it is not the master. the supply then increases its output voltage in an attempt to share more current. if two units have the same msb, they both continue to round 2 because either of them may be the master. round 2 in round 2, all supplies that are still communicating on the bus place their second msb on the share bus. if a supply senses that its msb is less than the value on the bus, it means that this supply must be a slave and it stops communicating on the share bus. round 3 to round 8 the same algorithm is repeated for up to eight rounds to allow supplies to compare their digital words and, in this way, to determine whether each unit is the master or a slave. digital share bus configuration the digital share bus can be configured in various ways. the bandwidth of the share bus loop is programmable in register 0xfe2b[2:0]. the extent to which a slave tries to match the current of the master is programmable in register 0xfe2a[3:0]. the slave moves up 1 lsb for every share bus transaction (eight data bits plus start and stop bits; see the description of register 0xfe2b in table 156). the master moves down x lsbs per share bus transaction, where x is the share bus setting in register 0xfe2a[7:4]. the maximum limit for the output voltage of the slave is 400 mv at the vs pins. the ishare_fault is set when the current share loop reaches its maximum value, that is, 400 mv at the vs pins. it is recommended that there be a load line of 5 m to 10 m between the output terminals of the power supply to the load. droop sharing the droop sharing functionality is implemented using the vout_droop command (register 0x28). using this command, a fixed amount of load line in mv/a can be applied to the output voltage. the output voltage is continuously sampled with a selectable rate (set in register 0xfe65[1:0]) before the droop is applied. under droop current sharing, the output voltage changes at a rate determined by the vout_transition_ rate command. setting 0xfe65[2] = 1 changes the internal voltage reference to the fastest internal supported rate. figure 61. how the share bus generates the digi tal word to place on the digital share bus current sense adc 1 lsb = 29.3v 35mv/29.3v = 1195 master + 35mv ? digital word digital filter 16 12 bits 1195 dec 0x4ab 8 bits 74 dec 0x4a 0x4a cs2+ cs2? v dd share bus 8-bit word 0xb5 8-bit word 0x4a ishare i out = 35a 1m ? psu a 12004-057 data sheet adp1055 rev. a | page 37 of 140 light load mode and d eep light load mode to facilitate a reduction of power loss at light loads, the adp1055 supports light load mode and deep light load mode. the threshold, speed, and hysteresis for deep light load mode are selectable in register 0xfe4b. in deep light load mode, a selectable set of pwm outputs can be disabled using register 0xfe4c. typical examples include shutting down the synchronous rectifiers or shutting down certain pwm outputs in an interleaved topology for phase shedding. figure 62. light load settings in the gui the threshold, speed, and hysteresis for light load mode are programmed in register 0xfe5f. in sr light load mode (sr llm), the synchronous rectifiers operate in the forward conduction mode only; that is, they are turned off during the freewheeling period of the switching period in a buck derived isolated topology (either half wave or full wave rectifier on the output). in this way, the loss associated with the diode drop of the mosfet is minimized by turning the channel of the mosfet on, as well as maintaining the output inductor in discontinuous conduction mode (dcm). the rising and falling edges of the synchronous rectifiers in sr llm are programmed in register 0xfe19 to register 0xfe1c. when entering sr llm from sr normal mode or deep llm, or when exiting sr llm to sr normal mode based on the hysteresis level, the sr edges move as programmed by the phase-in speed in register 0xfe5f[7:4]. the sr llm settings (register 0xfe19 to register 0xfe1c) determine the minimum and maximum rising and falling edges of the sr pwm outputs in sr llm mode. if the load demands a duty cycle between the minimum and maximum settings, the sr edges are adjusted according to the required duty cycle for outa to outd. to enable the deep light load mode, the light load mode threshold must be greater than zero. figure 63. overlay of all sr modes pulse skipping the adp1055 supports a pulse skipping mode in which a pwm pulse is not turned on for the entire switching period. pulse skipping can be activated by setting register 0xfe50[1] = 1. the adp1055 enters pulse skipping mode when the required duty cycle is less than the modulation value set in register 0xfe53. register 0xfe50[0] = 0 sets all modulated edges to the start of the switching period. in the case of negative edge modulation, this setting can cause the pwm outputs to be inverted; therefore, setting register 0xfe50[0] = 1 programs the device to make the pwm outputs = 0 v in pulse skipping. for topologies such as the full-bridge phase shifted topology, where two pwm outputs are on without modulation for half the switching period, the setting in register 0xfe50[4] allows the adp1055 to disable such pwm outputs whether modulation is enabled or not. soft stop the adp1055 supports soft stop functionality. soft stop can be enabled for normal shutdown of the power supply using the operation and on_off_config commands, as described in the power-up and power-down section. soft stop can also be enabled during a fault triggered condition using register 0xfe51[7:6]. the soft stop time is programmed using the toff_delay and toff_fall commands (register 0x64 and register 0x65). during soft stop, various faults such as otp, ovp, and gpio faults can be masked using register 0xfe47. to maintain a zero output voltage, the sr1 and sr2 pwm outputs can be programmed to stay on for an additional time (see the description of register 0xfe50[7:6] in table 193). duty cycle double update rate the adp1055 senses the output voltage just before the beginning of the switching period and, depending on the error voltage, the next duty cycle command is initiated. because a transient condition can occur at any time between switching periods, the one-cycle update of the duty cycle causes a phase loss that is equal to = 360 (t d f c ) where: t d is the combined delay of the adc sampling plus the loop calculations for the compensator plus any additional propagation delay. f c is the crossover frequency. the minimum delay for the system is d t sw because it is only after d t sw that the effect of the duty cycle command takes place. due to this phase loss (which increases as the crossover frequency approaches the switching frequency), the crossover frequency of the system cannot be widened with satisfactory phase margin. to reduce the phase loss, the adp1055 uses a double update rate for the duty cycle, whereby the output voltage is sampled just before half the switching period and the new duty cycle command is issued. in this way, the phase loss from two subsequent duty cycle commands is halved to d t sw /2. duty cycle double update rate is optional and is enabled by setting register 0xfe57[0] = 1. when using the duty cycle double update rate, it is recommended that duty balance also be enabled (register 0xfe57[7] = 1). 12004-058 12004-059 adp1055 data sheet rev. a | page 38 of 140 duty balance, volt-second balance, and flux balancing for power topologies that use the first and third quadrant of the bh curve, it is recommended that duty balance be enabled when using double update rate. due to the nature of double update rate, it is possible that the average magnetizing current (and therefore the flux density of the transformer core) is not zero, but is equal to some positive or negative dc level. to prevent flux walking and an imbalance in the transformer, a combination of the duty balance and volt-second balance features can be used. in interleaved topologies, the volt-second balance feature can also be used for current balancing to ensure that each interleaved phase contributes equal power. for example, if a full bridge topology requires the diagonal edges of the h bridge to be equalized, the algorithm for duty balance averages the duty cycle over several switching cycles. duty balance is a purely digital correction that is applied to the pwm edges based on past duty cycles and does not take into account any feedback from an adc, as is the case for volt-second balance. duty balance is enabled by setting register 0xfe57[7] = 1; the speed at which the duty cycle is balanced is controlled by setting register 0xfe57[5:4]. additionally, the extent to which duty cycle correction (maximum of 160 ns for duty balance and volt-second balance each) can take place is sp ecified using register 0xfe57[2:1]. volt-second balance uses a sample-and-hold circuit (patent pending) that samples the peak current during both halves of the switching period. this feature is configured using register 0xfe56. the recommended settings for using the volt-second balance feature are as follows. 1. use register 0xfe56 to set the positive and negative edges. bits[7:4] set the positive period of integration, and bits[3:0] set the negative period of integration. the edges are logically anded together. typically, the diagonal edges of the h bridge are balanced. for example, in a full bridge topology, a setting of 10010110 for register 0xfe56 causes the device to sample the peak current at the end of the logical and of outa and outd (peak 1) and the logical and of outb and outc (peak 2). if peak 1 > peak 2, the result is positive and the duty cycle of the selected edges is reduced. if peak 2 > peak 1, the result is negative and the duty cycle of the selected edges is increased. 2. apply edge correction. using the same example, negative edge correction is applied to outa and outd, whereas positive edge correction is applied to outb and outc. appropriate edge correction is applied to the sr outputs as well. 3. enable volt-second balance by setting register 0xfe25[6] = 1. this setting is gated by a go command (register 0xfe00). volt-second balance is automatically disabled when the voltage on the cs1 pin is below 25 mv. figure 64. volt-second balance with register 0xfe56 = 0x96 figure 65. volt-second balance with register 0xfe56 = 0x69 figure 66. simplified internal structure of the volt-second balance circuit 12004-060 12004-061 vs balance algorithm sample and hold with reset vs balance edge select registers pwm vin vout sr1 sr2 outa outb outc outd cs1 input adp1055 12004-115 data sheet adp1055 rev. a | page 39 of 140 fault responses and state machine mechanics when a potentially abnormal condition occurs in the power supply that is regulated by the adp1055 , a flag is asserted and the system waits for a programmed debounce time. if the flag is continuously asserted until the end of the debounce time, it is latched as a fault. the fault is then processed according to the programmed fault response setting. the fault is cleared only when the flag condition is removed. the debounce circuitry is reset when the flag condition is removed; until then the fault remains set. priority of faults the response to each fault is configurable and is based on a priority level (see table 7). a higher number indicates a higher priority. table 7. priority of faults priority fault and configured fault response 12 (highest) voltage fault: disable output 11 voltage fault: shutdown with no retry 10 current fault: shutdown with no retry 9 voltage fault: shutdown with limited retry 8 current fault: shutdown with limited retry 7 voltage fault: shutdown with unlimited retry 6 current fault: shutdown with unlimited retry 5 voltage fault: wait delay and shutdown with limited or unlimited retry 4 current fault: constant current with wait delay 3 current fault: constant current without tripping vout_lv 2 current fault: constant current mode 1 (lowest) voltage fault: ignore fault flags the adp1055 has an extensive set of flags that are set when certain limits, conditions, and thresholds are exceeded. the response to these flags is individually programmable. flags can be ignored or used to trigger actions such as turning off certain pwm outputs or entering constant current mode. flags can also be used to turn off the power supply. the adp1055 can be pro- grammed to respond when these flags are reset. the adp1055 also has a set of latched fault registers (register 0xfe8c to register 0xfe93). the latched fault registers have the same flags as the pmbus status_x commands (register 0x7a to register 0x80), but the flags in the latched registers remain set so that intermittent faults can be detected. the clear_faults command (register 0x03) clears the latched fault registers and resets all the flags. first fault id (ffid) the first fault id (ffid) information is used to capture the first fault that caused the system to shut down. register 0xfe95 contains the id of the first fault that caused the system to shut down. faults captured in the first fault id register have configured actions of shutdown immediate, shutdown with retries, and disable pwm outputs with watchdog timeout. the contents of register 0xfe95 cannot be overwritten unless the information is first cleared. the ffid can be cleared by the clear_faults command (register 0x03), by a power cycle of the device, or by a pson signal using register 0x01, register 0x02, or both. if the black box feature is enabled, the ffid can also be cleared when the information is saved into the black box. table 8. example first fault id scenarios test setup condition result ocp has retry/delay of 100 ms with priority 10, debounce = 0. ovp has retry/delay of 200 ms with priority 9, debounce = 0. ocp occurs at t = 0. ovp occurs at t = 10 ms. ocp fault is processed due to smaller debounce time (no retry time), as well as higher priority. ocp has retry/delay of 100 ms with priority 10, debounce = 0. ovp has retry/delay of 0 ms with priority 11, debounce = 0. ocp occurs at t = 0. ovp occurs at t = 10 ms. ocp fault is processed at t = 0; device waits 100 ms before action is taken. ocp fault is replaced by ovp, and then ovp fault is processed at t = 10 ms due to higher priority even though retry delay is larger. ocp has retry/delay of 100 ms with priority 8, debounce = 5 ms. ovp has retry/delay of 200 ms with priority 9, debounce = 100 ms. ocp occurs at t = 50 ms. ovp occurs at t = 0. ovp is registered as a fault at t = 100 ms. ocp is registered as a fault at t = 55 ms. however, at t = 100 ms, ocp loses priority and ovp is processed due to higher priority. exception: if delay of ocp was smaller (for example, 5 ms), then ocp action is processed. ocp has retry/delay of 100 ms with priority 8, debounce = 0. ovp has retry/delay of 200 ms with priority 7, debounce = 0. ocp occurs at t = 0. ovp occurs at t = 0. ocp fault is processed due to higher priority. adp1055 data sheet rev. a | page 40 of 140 using the priority of faults (see the priority of faults section), the fault that causes the adp1055 to shut down is the one stored in the ffid. for example, a configuration includes these faults: ? ovp fault with a delay of 100 ms and five retry times ? ocp fault with an action to shut down immediately with a 0 ms delay if the ovp fault occurs and after the third retry attempt, the ocp fault occurs, the ocp fault is stored in the ffid register. on the other hand, if all five ovp retries occur before the ocp fault occurs, the ovp fault is stored in the ffid. this statement is true only if register 0xfe_48[1:0] is set to 01. if it is set to 10, the ffid is set to ovp on the first retry time. note that warning flags such as iout_oc_warn and vout_ov_warn do not have debounce times. the adp1055 has a fault handler that can detect and track faults and, in the case where a fault is programmed to shut down and retry (restart) the system, the fault handler cycles the adp1055 through a shutdown and soft start procedure. throughout the soft start ramp, the fault handler continues to monitor the device for any faults that can trigger a fault response. soft start blanking can be configured to ignore faults during the soft start ramp. if a fault condition triggers a shutdown-retry cycle, the fault handler tracks the number of retry attempts of the programmed fault response and permanently shuts down the device when the configured number of retry times is reached. a shutdown-retry cycle is considered successful if the triggering fault is cleared at the end of the soft start ramp, at which point voltage regulation is achieved. following a successful retry attempt, the fault handler removes the fault from its queue, clears all retry attempt counters, and monitors the device for the next highest priority fault. debounce times can be added to a flag condition to effectively delay the fault condition beyond the end of the soft start ramp. note that the fault handler considers this a successful retry attempt (because no fault is seen when transitioning from soft start to normal operation). the fault handler clears the fault and resets the retry counters. for example, consider a ton_rise time of 10 ms, with a fault response set to shut down and retry three times, and a flag condition that occurs during the soft start ramp (t 1 < 10 ms). if the debounce time (t d ) is small enough such that t 1 + t d < ton_rise, the fault condition is latched before the end of the soft start ramp, and the adp1055 shuts down and retries accordingly, while incrementing the retry counter. after three retries, the adp1055 shuts down, requiring a power-up to start again. however, if the debounce time (t d ) is large enough such that t 1 + t d > ton_rise, the fault condition is latched after the adp1055 transitions from soft start to normal operation. in this scenario, the fault condition is cleared and the retry counter is reset at the end of the soft start ramp. the delayed fault initiates another set of three shutdown-retry cycles. this behavior effectively causes the system to retry indefinitely, even though the fault response is programmed to retry only three times. a notable exception is ton_max_fault when overshoot protection is enabled. if the adp1055 detects an out-of- regulation condition for x consecutive switching cycles during the soft start ramp (that is, the output voltage does not track the desired ramp-up voltage), the adp1055 tries to remedy the situation by exiting soft start and retrying. as a result, the soft start ramp ends prematurely, which has the effect of resetting the retry counter. table 9 provides a summary of faults and respective debounce times. fault condition during soft start and soft stop if a fault condition occurs during soft start, the controller responds as programmed unless the flag is blanked. flag blanking during soft start and soft stop is programmed in register 0xfe46 and register 0xf47, respectively. if a fault (for example, ton_max or iin_oc) occurs at any time during the soft start process with an action set to a value other than shutdown, the remainder of the soft start ramp continues at the transition rate specified by the pmbus command vout_transition_rate (register 0x27). during soft start, the ton_max fault is valid; after output regulation is reached, the uvp fault is valid. this means that the system does not start monitoring for uvp fault until after the soft-start ramp-up. watchdog timer in the case where the voltage fault response is set to disable the outputs and wait for the faults to clear (bits[7:6] = 11), the adp1055 disables the pwm outputs but does not immediately shut down and restart through a soft start cycle. the adp1055 keeps the pwm outputs disabled until the fault is cleared, after which the pwm outputs are reenabled. if the fault is not cleared, the system can potentially remain in a dormant condition for an infinitely long time. to prevent this condition, a watchdog timer can be set to time out the fault condition. the wdt_setting command (register 0xfe3f) is used to set a timeout of 0 sec, 1 sec, 5 sec, or 10 sec, after which the system shuts down, captures the ffid, and requires a power-up (ctrl pin or operation command) to restart. data sheet adp1055 rev. a | page 41 of 140 table 9. summary of faults with debounce times function/pmbus command pin comments debounce lsb fault response command vout_ov_fast ovp an analog comparat or on this pin provides this protec tion. 0xfe2f[1:0] vout_ov_fast_ response vout_ov vs the adc on this pin is averaged every 82 s with 7-bit accuracy for this fault. this information is compared with the vout_ov_fault_limit to set the flag. 0xfe30[3:0] 1.6/2 7 vout_ov_fault_ response vout_ov_warn vs same as vout_ov. n/a 1.6/2 7 n/a vout_uv_warn vs same as vout_uv. n/a 1.6/2 9 n/a vout_uv vs the adc on this pin is averaged every 328 s with 9-bit accuracy for this fault. this information is compared with the vout_uv_fault_limit to set the flag. 0xfe30[10:8] 1.6/2 9 vout_uv_fault_r esponse iout_oc cs2 the adc on this pin is averaged every 2.6 ms with 12-bit accuracy for this fault. this information is compared with the iout_oc_fault_limit to set the flag. 0xfe31[3:0] iout_oc: cs2_range/2 12 iout_oc_ fault_response the adc on this pin is averaged every 328 s with 9-bit accuracy for cc mode. this information is compared with the iout_oc_fault_limit the threshold set in register 0xfe5d[2:0] to enter cc mo de. for turbo mode, the averaging is every 41 s with an equivalent 6-bit resolution. cc mode: cs2_range/2 9 cc turbo mode: cs2_range/2 6 iout_oc_lv cs2 the adc on this pin is averaged every 10.5 ms with 12-bit accuracy for this fault. this information is compared with the iout_oc_lv_fault_limit to set the flag. 0xfe30[15:14] cs2_range/2 12 iout_oc_fast cs2 an analog comp arator on this pin provides this prot ection. 0xfe2d[1:0] iout_oc_fast_ fault_response iout_uc cs2 the adc on this pin is averaged every 10.5 ms with 12-bit accuracy for this fault. this information is compared with iout_uc_fault_limit to set the flag. 0xfe31[7:4] iout_uc: cs2_range/2 12 iout_uc_fault_ response the adc on this pin is averaged every 328 s with 9-bit accuracy for constant current mode. this information is compared with the iout_uc_fault_limit the threshold set in register 0xfe5d[2:0] to enter cc mode. for turbo mode, the averaging is every 41 s with an equivalent 6-bit resolution. cc mode: cs2_range/2 9 cc turbo mode: cs2_range/2 6 iout_uc_fast cs2 an analog comp arator on this pin provides this prot ection. 0xfe2e[0] iout_uc_fast_ fault_response iin_oc cs1 the adc on this pin is averaged every 10.5 ms with 12-bit accuracy for this fault. this information is compared with the iout_oc_fault_limit to set the flag. 0xfe31[11:8] 1.6/2 12 iin_oc_fault_ response iin_oc_fast cs1 an analog comparator on this pin pr ovides this protection. 0x fe2c[1:0] iin_oc_fast_ fault_response ishare cs2 when maximum limit to change output voltage is reached. 0xfe31[15:12] ishare_fault_ response iout_oc_warn cs2 same as iout_oc. n/a cs2_range/2 12 vin_low vff the adc on this pin is averaged every 328 s with 9-bit accuracy for this fault. this information is compared with the vin_low to set the flag. 1.6/2 9 vin_uv vff the adc on this pin is averaged every 328 s with 9-bit accuracy for this fault. this information is compared with the vin_uv_fault_limit to set the flag. 0xfe30[13:11] 1.6/2 9 vin_uv_fault_ response vin_uv_warn vff same as vin_uv. n/a n/a vin_ov vff the adc on this pin is averaged every 328 s with 9-bit accuracy for this fault. this information is compared with the vin_ov_fault_limit to set the flag. 0xfe30[7:4] 1.6/2 9 vin_ov_fault_ response vin_ov_warn vff same as vin_ov. n/a pout_op n/a the multiplication of vs and cs2 adcs averaged every 2.6 ms with 11-bit accuracy for this fault. this information is compared with the pout_op_fault_limit to set the flag. 0xfe32[11:8] pout_op_fault_ response adp1055 data sheet rev. a | page 42 of 140 function/pmbus command pin comments debounce lsb fault response command ot n/a the adc on this pin is averaged every 200 ms with 14-bit accuracy for this fault to provide two consecutive readings (external forward and external reverse temperature sensors). this information is compared with the ot_fault_limit to set the fl ag. if external reverse is disabled, the averaging is performed every 130 ms. 0xfe32[3:0] ot_fault_ response ot_warn n/a same as ot. n/a gpiox_fault gpiox immediate. 0xfe32[15:0] gpiox_fault_ response ton_max n/a immediate. 0xfe32[7:4] 1.6/2 9 for vs ton_max_fault_ response ton_max_warn n/a n/a 1.6/2 9 for vs vdd/vcore_ov vdd vcore immediate. 0xfe4d[5] 0xfe4d[6] vdd uv vdd immediate. 0xfe4d[4] shutdown standard pmbus flags figure 67 shows the standard pmbus flags supported by the adp1055 . figure 67. standard pmbus flags supported by the adp1055 7 reserved 6 reserved 5 input a fuse/breaker fault 4 input b fuse/breaker fault 3 input a or-ing device fault 2 input b or-ing device fault 1 output or-ing device fault 0 reserved status_other 7 vout 6 iout/pout 5 input 4 mfr_specific 3 power_good 2 fans 1 other 0 unknown 7 busy 6 off 5 vout_ov_fault 4 iout_oc_fault 3 vin_uv_fault 2 temperature 1 cml 0 none of the above status_word (upper byte) status_byte also is the lower byte of status_word 7 vout_ov_fault 6 vout_ov_warning 5 vout_uv_warning 4 vout_uv_fault 3 vout_max warning 2 ton_max_fault 1 toff_max_warning 0 vout tracking error 7 iout_oc_fault 6 iout_oc_lv_fault 5 iout_oc_warning 4 iout_uc_fault 3 current share fault 2 in power limiting mode 1 pout_op_fault 0 pout_op_warning 7 ot_fault 6 ot_warning 5 ut_warning 4 ut_fault 3 reserved 2 reserved 1 reserved 0 reserved status_temperature status_iout status_vout 7 invalid/unsupported command 6 invalid/unsupported data 5 packet error check failed 4 memory fault detected 3 processor fault detected 2 reserved 1 other communication fault 0 other memory or logic fault status_cml 7 vin_ov_fault 6 vin_ov_warning 5 vin_uv_warning 4 vin_uv_fault 3 unit off for low input voltage 2 iin_oc_fault 1 iin_oc_warning 0 pin_op_warning status_input 7gpio4 6gpio3 5gpio2 4gpio1 3 iin_oc_fast_fault 2 iout_uc_fast_fault 1 iout_oc_fast_fault 0 vout_ov_fast status_mfr_specific 15 eeprom unlocked 14 adaptive dead time 13 soft start filter 12 soft start ramp 11 modulation limit 10 volt-sec balance limit 9 light_load_mode (llm) 8 constant current status_mfr_unknown 7 pgood2_fault 6 pgood1_fault 5 sync_unlock 4 sr off address_warning 3 2 vcore_ov 1 vdd_ov 0vdd_uv 12004-062 data sheet adp1055 rev. a | page 43 of 140 black box feature black box operation the adp1055 supports a configurable black box feature. using this feature, the device records to the eeprom vital data about the faults that cause the system to shut down. two dedicated eeprom pages are used for this purpose: page 2 and page 3. when the adp1055 encounters a fault with the action to shut down the device, a snapshot of the current telemetry is taken, as well as the first fault that caused the shutdown (see figure 68). if the black box feature is enabled, this information is saved to the eeprom before the device shuts down. figure 68. black box write operation this black box feature is extremely helpful in troubleshooting a failed system during testing and evaluation. if a system is recalled for failure analysis, it is possible to read this information from the eeprom to help investigate the root cause of the failure. only a limited number of writes to the eeprom are allowed. using register 0xfe48[1:0], the user can set the level of infor- mation that is logged in the black box, as follows: ? no recording. ? only record telemetry just before the final shutdown. ? record telemetry of final shutdown and all intermittent retry attempts (if device is set to shut down and retry). ? record telemetry of final shutdown, all retry attempts, and normal power-down operations using the ctrl pin or the operation command. using register 0xfe48[2], the user can program the maximum number of records to 158,000 (recommended when the ambient temperature of the adp1055 is less than 85c) or to 16,000 (when the ambient temperature of the adp1055 is less than 125c). if the number of records exceeds the programmed value, the recording of data to the eeprom is halted and the status_cml bit (register 0x7e[0]) is set and remains set. data accumulated after the limit is reached is not reliable and should be ignored. if a device experiences multiple concurrent faults, the id of the first fault that triggers the system to shut down is captured in the first_fault_id register (register 0xfe95). the ffid and all flag status and telemetry data are captured in the black box at every write to the black box (see the black box contents section for a list of the data saved). the last valid byte of each record is a pec byte, which is used to calculate the validity of each record stored in the eeprom. following each recording, the record number (rec_no) is incremented, and this number is compared to the maximum allowed number of records. if rec_no equals the maximum record number (158,000 or 16,000), no additional black box recording is allowed because the eeprom has reached its maximum allowed erase program cycles and any additional recording is unreliable. black box contents page 2 and page 3 of the eeprom are reserved for black box operation. the size of each eeprom page is 512 bytes; each page is composed of eight records with 64 bytes each. page 2 and page 3 combined give a total of 16 records, which function as a circular buffer for recording black box information. the eeprom is a page erase memory, and an entire page must be erased before the page can be written to. due to the page erase requirement of the eeprom, after writing the eighth record of any page, the next page is automatically erased to allow for continuous black box recording. each time a record is written in the black box, the device increments the record number. each eeprom write records the registers listed in table 10. pec byte the packet error checking (pec) byte at the end of each black box record is specific to each record and is calculated using a crc-8 polynomial: c(x) = x 8 + x 2 + x 1 + 1. the pec byte is calculated on the first four bytes of each record (called the header block), one byte at a time. in a write to eeprom, the pec byte is appended to the data and is the last valid byte of that record. in a read from eeprom, the header block of each record is used to calculate an expected pec code, and this internally calculated pec code is compared to the received pec byte. if the comparison fails, the pec_err bit (status_ cml[5]) is set, and that record is discarded because the validity of the data has been compromised. 12004-063 v out pwm fault detected shutdown debounce write adp1055 data sheet rev. a | page 44 of 140 table 10. contents of black box records byte register address register name header block 1 rec_no[7:0] 2 rec_no[15:8] 3 rec_no[23:16] 4 0xfe95 first_fault_id[7:0] data block 5 0x78 status_word[7:0] (same as status_byte[7:0]) 6 0x79 status_word[15:8] 7 0x7a status_vout 8 0x7b status_iout 9 0x7c status_input 10 0x7d status_temperature 11 0x7e status_cml 12 0x7f status_other 13 0x80 status_mfr_specific 14 0xfe94 status_unknown[7:0] 15 0xfe94 status_unknown[15:8] 16 0x88 read_vin[7:0] 17 0x88 read_vin[15:8] 18 0x89 read_iin[7:0] 19 0x89 read_iin[15:8] 20 0x8b read_vout[7:0] 21 0x8b read_vout[15:8] 22 0x8c read_iout[7:0] 23 0x8c read_iout[15:8] 24 0x8d reserved[7:0] 25 0x8d reserved[15:8] 26 0x8e read_temperature_2[7:0] 27 0x8e read_temperature_2[15:8] 28 0x8f read_temperature_3[7:0] 29 0x8f read_temperature_3[15:8] 30 0x94 read_duty_cycle[7:0] 31 0x94 read_duty_cycle[15:8] 32 0x95 read_frequency[7:0] 33 0x95 read_frequency[15:8] 34 0x96 read_pout[7:0] 35 0x96 read_pout[15:8] pec block 36 pec[7:0] undefined block 37 64 black box timing two eeprom pages (page 2 and page 3) are used to store the black box data; each page contains eight records. due to the page erase requirement of the eeprom, when the black box has completed writing the last record to either page (rec_no = 8n ? 1; n > 0, that is, 7, 15, 23, 31, and so on), a page erase operation is automatically initiated on the other page. the erase operation takes an additional 32 ms to complete. during the erase operation, any pmbus transaction to the device receives a no acknowledge (nack), and the busy bit (bit 7) of status_byte is set accordingly. at the end of the erase operation, the device resumes normal operation. the minimum time required to program a complete black box record is calculated as follows: t prog_bbox (min) = ( num_of_bytes + 1) t prog where: t prog = 30.72 s. num_of_bytes = 36 (36 bytes in each black box record). if the erase operation is part of the sequence of saving data to the black box, the additional erase time is added to t prog_bbox (min) , as follows: t prog_bbox (min) = ~1.2 ms t erase = ~32 ms t prog_bbox (max) = ~33.2 ms when black box writing is enabled with the option to record retry attempts (register 0xfe48[1:0] = 10 or 11), data can be saved between every unsuccessful attempt to restart the device. it is recommended that the minimum retry time be set to a value greater than 1.2 ms. if the retry time is insufficient for black box recording, the device prolongs the retry time so that the recording can finish before attempting to restart the power supply. this delay may result in inconsistent retry times between successive restart attempts. the retry time is programmed using the pmbus commands xxx_fault_response, where xxx refers to the various configurable faults for that device. at every eighth recording, the t erase time is added to the t prog_bbox (min) time, resulting in the t prog_bbox (max) time. if the retry time is less than the maximum time, the device again delays the restart attempt to wait for the completion of the black box recording and the successive page erase. black box operation is a direct result of a fault condition that triggers a power supply shutdown. to ensure that the black box is written to in the event of a brownout condition, a holdup capacitor on the vdd pin is recommended to ensure that all the information is written to the black box before the adp1055 reaches the uvlo threshold. (instead of a holdup capacitor, an equivalent capacitor from the rail where 3.3 v is derived can be used to maintain the vdd voltage above uvlo.) the capacitor must be large enough to maintain power to the system over a time that exceeds t prog_bbox (min) which is approximately 10 f on a 10 v rail until vdd falls below uvlo. data sheet adp1055 rev. a | page 45 of 140 black box readback two dedicated commands can be used to read back the contents of the black box data stored in the eeprom. the read_ blackbox_curr command (register 0xf2) is a block read command that returns the current record n (last record saved) with all related data, as defined in the black box contents section. the read_blackbox_prev command (register 0xf3) is a block read command that returns the data for the previous record n ? 1 (next-to-last record saved). because these commands are block read commands, the first byte received is called the byte_count and indicates to the pmbus master how many more bytes to read. in the adp1055 , byte_count = 36. for information about how to read from the eeprom directly using these commands, see the read operation (byte read and block read) section. it is recommended that the gui be used to read back the contents of the black box; the black box data is readily available in the gui, which displays the data in a graphical format. black box power sequencing when the adp1055 is powered up, the contents of the user settings in the eeprom are downloaded into the internal registers. immediately after this, the contents of the black box data (that is, page 2 and page 3) are read from the eeprom by the device to determine the last valid rec_no saved and to determine whether a page erase operation is required before starting up the device in normal mode. if the highest rec_no is located on the last record of either page (that is, the next record to store data is at the start of the other page) and the other page has not been erased, the adp1055 automatically initiates a page erase to the other page to prepare it for further black box recording. the adp1055 performs a soft start sequence only after the page erase is completed. adp1055 data sheet rev. a | page 46 of 140 power supply calibration and trim the adp1055 allows the entire power supply to be calibrated and trimmed digitally in the production environment. the device can calibrate items including the output voltage, input voltage, input current, and input power, and it can trim for tolerance errors introduced by sense resistors, current transformers, and resistor dividers, as well as for its own internal circuitry. the adp1055 is factory trimmed, but it can be retrimmed by the user to compensate for the errors introduced by external components. the adp1055 gui allows the user to revert the trim settings to their factory default values using the restore_ default_all command (register 0x12). to unlock the trim registers for write access, perform consecutive writes to trim_ password (register 0xd6) using the correct password. this password is the same one used to unlock the eeprom using eeprom_password (register 0xd5). the factory default password is 0xff. the adp1055 allows the user enough trim capability to trim for external components with a tolerance of 0.5% or better. if the adp1055 is not trimmed in the production environment, it is recommended that components with a tolerance of 0.1% or better be used for the inputs to cs1, vff, and vs to meet the data sheet specifications. voltage calibration and trim the voltage sense point can be calibrated digitally to minimize errors due to external components using the vout_trim command (register 0x22). this calibration can be performed in the production environment, and the settings can be stored in the eeprom of the adp1055 . the voltage sense inputs are optimized for sensing signals at 1 v. in a 12 v system, a 12:1 resistor divider is required to reduce the 12 v signal down to 1 v. it is recommended that the output voltage of the power supply be reduced to 1 v at this pin for best performance. the tolerance of the resistor divider introduces errors that must be trimmed. the adp1055 has enough trim range to trim out errors introduced by resistors with a tolerance of 0.5% or better. the vs adc produces a digital code equal to vs/1.6 4096. the vs inputs require a gain trim. the following steps should be performed before any other trim routine. 1. set the output regulation point to 100% of the nominal value. 2. enable the power supply with no load current. the power supply output voltage is divided down by the resistor divider to give 1 v across the vs+ and vs? differential input pins. 3. adjust the vs trim register (register 0xfe80) until the vs voltage value in register 0xfe97[13:2] reads 1010 0000 0000 when there is 1.0 v on the pins. cs1 trim the current sense can be calibrated using a dc or ac signal to minimize errors due to external components. using a dc signal a known voltage (vx) is applied at the cs1 pin. the cs1 adc should output a digital code equal to vx/1.6 4096. adjust the cs1 gain trim register (register 0xfe82) until the cs1 adc value in register 0xfe98 reads the correct digital code. for example, register 0xfe98[13:2] reads a value of 1010 0000 0000 when there is 1.0 v on the cs1 pin. using an ac signal a known current (ix) is applied to the cs1 pin. this current passes through a current transformer, a diode rectifier, and an external resistor (r cs1 ) to convert the current information to a voltage (vx). this voltage is fed into the cs1 pin. the voltage (vx) is calculated as follows: vx = ix ( n1/ n2) r cs1 where n1 / n2 is the turns ratio of the current transformer. the cs1 adc outputs a digital code equal to vx/1.6 4096. adjust the cs1 gain trim register (register 0xfe82) until the cs1 adc value in register 0xfe98 reads the correct digital code. vff calibration and trim the vff feedforward adc (see figure 32) is used for voltage line feedforward and is factory trimmed. this adc cannot be trimmed by the user. the vff slow adc requires a gain trim. 1. enable the power supply with full load current at the nominal input voltage. the secondary peak reverse voltage on the output rectifiers is filtered by an external rcd circuit (see figure 32). 2. to trim the vff adc, reverse-calculate the primary voltage as follows: v primary = vx ( r1 + r2 )/ r2 (n1/ n2) where: vx is the voltage at the vff pin. n1 / n2 is the turns ratio. } 3. adjust the vff gain trim register (register 0xfe81) until this calculated voltage is equal to the desired primary input voltage. for example, register 0xfe96[13:2] reads a value of 1010 0000 0000 when there is 1.0 v on the vff pin. the resistors in figure 32 are sized such that the first time constant, rc, is long enough to prevent overcharging of the capacitor (roughly 200 ns in a typical application), whereas the second time constant, (r1 + r2) c, is long enough to keep the average voltage constant during the rectifier off time. data sheet adp1055 rev. a | page 47 of 140 pmbus digital communication the pmbus slave with pec allows a device to interface to a pmbus compliant master device, as specified by the pmbus power system management protocol specification (revision 1.2, september 6, 2010). the pmbus slave is a 2-wire interface that can be used to communicate with other pmbus compliant devices and is compatible in a multimaster, multislave bus configuration. the pmbus slave can communicate with master pmbus devices that support packet error checking (pec), as well as with master devices that do not support pec. features the function of the pmbus slave is to decode the command sent from the master device and respond as requested. communication is established using an i 2 c-like 2-wire interface with a clock line (scl) and data line (sda). the pmbus slave is designed to externally move chunks of 8-bit data (bytes) while maintaining compliance with the pmbus protocol. the pmbus protocol is based on the smbus specification (version 2.0, august 2000). the smbus specification is, in turn, based on the philips i 2 c bus specification (version 2.1, january 2000). the pmbus incorporates the following features: ? slave operation on multiple device systems ? 7-bit addressing ? 100 kbits/sec and 400 kbits/sec data rates ? packet error checking ? support for the group command protocol ? support for the alert response address protocol with arbitration ? general call address support ? support for clock low extension (clock stretching) ? separate multiple byte receive and transmit fifo ? extensive fault monitoring overview the pmbus slave module is a 2-wire interface that can be used to communicate with other pmbus compliant devices. its transfer protocol is based on the philips i 2 c transfer mechanism. the adp1055 is always configured as a slave device in the overall system. the adp1055 communicates with the master device using one data pin (sda) and one clock pin (scl). because the adp1055 is a slave device, it cannot generate the clock signal. however, it is capable of clock-stretching the scl line to put the master device in a wait state when it is not ready to respond to the masters request. communication is initiated when the master device sends a command to the pmbus slave device. commands can be read or write commands, in which case data is transferred between the devices in a byte wide format. commands can also be send commands, in which case the command is executed by the slave device upon receiving the stop bit. the stop bit is the last bit in a complete data transfer, as defined in the pmbus/smbus/i 2 c communication protocol. during communication, the master and slave devices send acknowledge or no acknowledge bits as a method of handshaking between devices. in addition, the pmbus slave on the adp1055 supports packet error checking (pec) to improve reliability and communication robustness. the adp1055 can communicate with master pmbus devices that support pec, as well as with master devices that do not support pec. see the smbus specification for a more detailed description of the communication protocol. when communicating with the master device, it is possible for illegal or corrupted data to be received by the pmbus slave device. in this case, the pmbus slave device should respond to the invalid command or data, as defined by the pmbus specification, and indicate to the master device that an error or fault condition has occurred. this method of handshaking can be used as a first level of defense against inadvertent programming of the slave device that can potentially damage the chip or system. the pmbus specification defines a set of generic pmbus commands that is recommended for a power management system. however, each pmbus device manufacturer can choose to implement and support certain commands as it deems fit for its system. in addition, the pmbus device manufacturer can choose to implement manufacturer-specific commands whose functions are not included in the generic pmbus command set. the list of standard pmbus an d manufacturer-specific commands can be found in the standard pmbus commands supported by the adp1055 section and manufacturer specific commands section. transfer protocol the pmbus slave follows the transfer protocol of the smbus specification (version 2.0), which is based on the fundamental transfer protocol format of the philips i 2 c bus specification (version 2.1). data transfers are byte wide, lower byte first. each byte is transmitted serially, most significant bit (msb) first. figure 69 shows a basic transfer. figure 69. basic data transfer for an in-depth discussion of the transfer protocols, see the smbus and i 2 c specifications. s 7-bit address r/w a a... p 8-bit data = master-to-slave = slave-to-master 12004-064 adp1055 data sheet rev. a | page 48 of 140 data transfer commands data transfer using the pmbus slave is established using pmbus commands. the pmbus specification requires that all pmbus commands start with a slave address with the r/ w bit cleared (set to 0), followed by the command code. (the only exception is smbalrt alert response address protocol.) all pmbus commands supported by the adp1055 device follow one of the protocol types shown in figure 70 to figure 77 . (for pmbus master devices that do not support pec, the pec byte is removed.) figure 70 to figure 77 use the following abbreviations: ? s = start condition ? p = stop condition ? sr = repeated start condition ? w = write bit (0) ? r = read bit (1) ? a = acknowledge bit (0) ? na = no acknowledge bit (1) figure 70. send protocol with pec figure 71. write byte protocol with pec figure 72. write word protocol with pec figure 73. read byte protocol with pec figure 74. read word protocol with pec figure 75. block write protocol with pec figure 76. block read protocol with pec figure 77. block write and block read protocol with pec the pmbus slave module of the adp1055 also supports manufacturer-specific extended commands. these commands follow the same protocol as the standard pmbus commands. however, the command code consists of two bytes: ? command code extension: 0xfe ? extended command code: 0x00 to 0xff using the manufacturer-specific extended commands, the pmbus device manufacturer can add an additional 256 manufacturer- specific commands to its pmbus command set. s 7-bit slave address w a a a p command code pec byte = master-to-slave = slave-to-master 12004-065 s 7-bit slave address w a a a a p command code data byte pec byte = master-to-slave = slave-to-master 12004-066 s 7-bit slave address w a a a a a p command code data byte low data byte high pec byte = master-to-slave = slave-to-master 12004-067 s 7-bit slave address 7-bit slave address w a a a r a a p command code sr pec byte data byte = master-to-slave = slave-to-master 12004-068 s 7-bit slave address 7-bit slave address w a a a r a p a na command code sr pec byte data byte low data byte high = master-to-slave = slave-to-master 12004-069 s 7-bit slave address byte count = m w . . . a a a a a a p command code pec byte data byte 1 data byte m = master-to-slave = slave-to-master 12004-070 s 7-bit slave address 7-bit slave address w sr a a a a a a p na pec byte r command code data byte 1 data byte n byte count = n = master-to-slave = slave-to-master 12004-071 . . . a a data byte 1 data byte n byte count = n = master-to-slave = slave-to-master 12004-072 . . . . . . a a 7-bit slave address sr a r data byte 1 data byte m s 7-bit slave address byte count = m w a a a command code a p na pec byte data sheet adp1055 rev. a | page 49 of 140 group command protocol in addition to the communication protocols described in the data transfer commands section, the pmbus slave supports a special group command in which commands are sent to multiple slaves in a single serial transmission. the commands to each slave can be different from one another, with each set of {slave- address, command} separated by a repeated start (sr) bit (see figure 78). at the end of a transmission to all slaves, a single stop (p) bit is sent to initiate concurrent execution of the received commands by all slaves. note that the pec byte transmitted to each slave is calculated using only its slave address, command code, and data bytes. figure 78. group command protocol with pec clock generation and stretching the adp1055 is always a pmbus slave device in the overall system; therefore, the device never needs to generate the clock, which is done by the master device in the system. however, the pmbus slave device is capable of clock stretching to put the master in a wait state. by stretching the scl signal during the low period, the slave device communicates to the master device that it is not ready and that the master device must wait. conditions where the pmbus slave device stretches the scl line low include the following: ? master device is transmitting at a higher baud rate than the slave device. ? receive fifo buffer of the slave device is full and must be read before continuing to prevent a data overflow condition. ? slave device is not ready to send data that the master has requested. note that the slave device can stretch the scl line only during the low period. also, whereas the i 2 c specification allows indefinite stretching of the scl line, the pmbus specification limits the maximum time that the scl line can be stretched, or held low, to 25 ms, after which the adp1055 must release the communica- tion lines and reset its state machine. start and stop conditions start and stop conditions involve serial data transitions while the serial clock is at a logic high level. the pmbus slave device monitors the sda and scl lines to detect the start and stop conditions and transition its internal state machine accordingly. figure 79 shows typical start and stop conditions. figure 79. start and stop transitions repeated start condition in general, a repeated start (sr) condition is the absence of a stop condition between two transfers. the pmbus communication protocol makes use of the repeated start condition only when performing a read access (read byte, read word, and block read). other uses of the repeated start condition are not allowed. general call support the pmbus slave is capable of decoding and acknowledging a general call address. the pmbus device responds to both its own address and the general call address (0x00). note that all pmbus commands must start with the slave address with the r/ w bit cleared (set to 0), followed by the command code. this is also true when using the general call address to communi- cate with the pmbus slave device. the only exception to this rule is when the smbalrt alert response address is used. alert response address (ara) if a pmbus slave device supports the smbalrt hardware pin to interrupt the master on a fault condition, the smbus alert response address protocol must be supported to allow commu- nication between the master and slave on the device that triggers the fault. when the smbalrt pin on the slave is asserted, the master queries the address of the slave device that triggered the fault by sending the alert response address (0001 to 100x). in response to this address, the slave with the asserted smbalrt pin acknowledges (acks) the address and responds with its own slave address (7-bit address and plus 0). if multiple slave devices have their smbalrt pins asserted, the slave with the lowest address wins the arbitration and subsequently deasserts its smbalrt pin. figure 80. ara protocol with pec s slave 1 address slave 2 address data 1 . . . n w a a a command code 1 pec 1 sr data 1 . . . n w a a a a a a command code 2 pec 2 slave m address sr data 1 . . . n w a a p a command code m pec m = master-to-slave = slave-to-master 12004-073 12004-074 s 7-bit ara x a a a p slave address pec byte = master-to-slave = slave-to-master 12004-075 adp1055 data sheet rev. a | page 50 of 140 pmbus address selection control of the adp1055 is implemented via the i 2 c interface. the adp1055 device is connected to the i 2 c bus as a slave device under the control of a master device. the pmbus address of the adp1055 is set by connecting an external resistor from the add pin to agnd. table 11 lists the recommended resistor values and associated pmbus addresses. table 11. pmbus address settings pmbus addr 1 pmbus addr 2 pmbus addr 3 pmbus addr 4 1% resistor () (e96 series) 0x40 0x50 0x60 0x70 210 (or connect to agnd) 0x41 0x51 0x61 0x71 750 0x42 0x52 0x62 0x72 1330 0x43 0x53 0x63 0x73 2050 0x44 0x54 0x64 0x74 2670 0x45 0x55 0x65 0x75 3570 0x46 0x56 0x66 0x76 4420 0x47 0x57 0x67 0x77 5360 0x48 0x58 0x68 0x78 6340 0x49 0x59 0x69 0x79 7320 0x4a 0x5a 0x6a 0x7a 8450 0x4b 0x5b 0x6b 0x7b 9530 0x4c 0x5c 0x6c 0x7c 10,700 0x4d 0x5d 0x6d 0x7d 12,100 0x4e 0x5e 0x6e 0x7e 13,700 0x4f 0x5f 0x6f 0x7f 15,000 (or connect to vdd) using a resistor enables the selection of 16 different base addresses from 0x40 to 0x4f. additional addresses can be selected using the slv_addr_select command (register 0xd0). for example, a device can be programmed to have an address of 0x65 by connecting a 3.57 k resistor at the add pin and programming register 0xd0[5:4] to 10 and saving to the eeprom. the next time that the power is cycled to the adp1055 , the device responds to an address of 0x65. other addresses can be selected. if an incorrect resistor value is used and the resulting i 2 c address is close to a threshold between two addresses, the status_unknown flag is set (register 0xfe94[3]). it is recommended that 1% tolerance resistors be used on the add pin. however, 5% resistors can be selected, but the use of some of the addresses will not be allowed due to the overlap of address ranges. in addition to its programmed address, the adp1055 responds to the standard pmbus broadcast address (general call) of 0x00. fast mode fast mode (400 khz) uses essentially the same mechanics as the standard mode of operation; the electrical specifications and timing are most affected. the pmbus slave is capable of communicating with a master device operating in standard mode (100 khz) or fast mode. 10-bit addressing the pmbus slave device does not support 10-bit addressing as defined in the i 2 c specification. packet error checking the pmbus controller implements packet error checking (pec) to improve reliability and communication robustness. packet error checking is implemented by appending a pec byte at the end of the message transfer. the pec byte is calculated using a crc-8 algorithm on all addr, cmd, and data bytes from the start to stop bits (excluding the ack, nack, start, restart, and stop bits). the pec byte is appended to the end of the message by the device that supplied the last data byte. the receiver of the pec byte is responsible for calculating its internal pec code and comparing it to the received pec byte. the adp1055 can communicate with master pmbus devices that support pec, as well as with master devices that do not support pec. if a pec byte is available, the pmbus device checks the pec byte and issues an acknowledge (ack) if the pec byte is correct. if the pec byte comparison fails, the pmbus device issues a no acknowledge (nack) in response to the pec byte and does not process the command sent from the master. the pmbus device uses built-in hardware to calculate the pec code using the crc-8 polynomial, c(x) = x 8 + x 2 + x 1 + 1. the pec code is calculated one byte at a time, in the order that it is received. in a read transaction, the pmbus device appends the pec byte following the last data byte. in a write transaction, the pmbus device compares the received pec byte to the internally calculated pec code. electrical specifications all logic complies with the electrical specification outlined in the pmbus power system management protocol specification part 1 , revision 1.2, dated september 6, 2010. fault conditions the pmbus protocol provides a comprehensive set of fault conditions that must be monitored and reported. these fault conditions can be grouped into two major categories: commu- nication faults and monitoring faults. communication faults are error conditions associated with the data transfer mechanism of the pmbus protocol (see the following sections for more information). monitoring faults are error conditions associated with the operation of the pmbus device, such as output overvoltage protection, and are specific to each pmbus device. for more information about the monitoring fault conditions, see the fault responses and state machine mechanics section. data sheet adp1055 rev. a | page 51 of 140 timeout conditions the smbus specification, version 2.0, includes three clock stretching specifications related to timeout conditions. the timeout conditions are described in the following sections. t timeout a timeout condition occurs if any single scl clock pulse is held low for longer than the t timeout min of 25 ms. upon detecting the timeout condition, the pmbus slave device has 10 ms to abort the transfer, release the bus lines, and be ready to accept a new start condition. the device initiating the timeout is required to hold the scl clock line low for at least t timeout max = 35 ms, guaranteeing that the slave device is given enough time to reset its communication protocol. t low:sext the t low:sext = 25 ms specification is defined as the cumulative time that the scl line is held low by the slave device in any one message from the start to the stop condition. the pmbus slave device is guaranteed by design not to violate this specification. if the slave device violates this specification, the master is allowed to abort the transaction in progress and issue a stop condition at the conclusion of the byte transfer in progress. t low:mext the t low:mext = 10 ms specification is defined as the cumulative time that the scl line is held low by the master device in any one byte of a message between the start-to-acknowledge, acknowledge- to-acknowledge, or acknowledge-to-stop. if this specification is violated, the pmbus device treats it as a timeout condition and aborts the transfer. this check is not implemented in the adp1055 . data transmission faults data transmission faults occur when two communicating devices violate the pmbus communication protocol. the following items are taken from the pmbus specification (revision 1.2, september 6, 2010). see the pmbus specification for more information about each fault condition. corrupted data, pec (item 10.8.1) this item refers to parity error checking. the pmbus slave device compares the received pec byte with the calculated expected pec byte of each transmission, starting from the start bit to the stop bit. if the comparison fails, it responds as follows: ? send a no acknowledge (nack) for the pec byte. ? flush and ignore the received command and data. ? set the cml bit (bit 1) in the status_byte register. ? set the pec bit (bit 5) in the status_cml register. ? notify the host through smbalrt , if enabled. sending too few bits (item 10.8.2) transmission is interrupted by a start or stop condition before a complete byte (eight bits) has been sent. not supported; any transmitted data is ignored. reading too few bits (item 10.8.3) transmission is interrupted by a start or stop condition before a complete byte (eight bits) has been read. not supported; any received data is ignored. hosts sends or reads too few bytes (item 10.8.4) if a host ends a packet with a stop condition before the required bytes are sent/received, it is assumed that the host intended to stop the transfer. therefore, the pmbus slave does not consider this to be an error and takes no action, except to flush any remaining bytes in the transmit fifo. host sends too many bytes (item 10.8.5) if a host sends more bytes than are expected for the corresponding command, the pmbus slave considers this a data transmission fault and responds as follows: ? send a no acknowledge (nack) for all unexpected bytes as they are received. ? flush and ignore the received command and data. ? sets the cml bit (bit 1) in the status_byte register. ? set the invalid/unsupported data bit (bit 6) in the status_cml register. ? notify the host through smbalrt , if enabled. host reads too many bytes (item 10.8.6) if a host reads more bytes than are expected for the corresponding command, the pmbus slave considers this a data transmission fault and responds as follows: ? send all 1s (0xff) as long as the host continues to request data. ? set the cml bit (bit 1) in the status_byte register. ? set the other bit (bit 1) in the status_cml register. ? notify host through smbalrt , if enabled. device busy (item 10.8.7) pmbus slave device is too busy to respond to a request from the master device. this error can occur if the slave device is busy accessing the eeprom (for example, erasing a page, downloading from eeprom, or uploading to eeprom). the pmbus slave considers this a data transmission fault and responds as follows: ? send an acknowledge (ack) for the address byte. ? send a no acknowledge (nack) for the command and data bytes. ? send all 1s (0xff) as long as the host continues to request data. ? set the busy bit (bit 7) in the status_byte register. ? notify the host through smbalrt , if enabled. adp1055 data sheet rev. a | page 52 of 140 data content faults data content faults occur when data transmission is successful, but the pmbus slave device cannot process the data that is received from the master device. improperly set read bit in th e address byte (item 10.9.1) all pmbus commands start with a slave address with the r/ w bit cleared to 0, followed by the command code. the only exception is the transmission of the smbus alert response address (0001 to 100x). if a host starts a pmbus transaction with r/ w set in the address phase (equivalent to an i 2 c read), the pmbus slave considers this a data content fault and responds as follows: ? send an acknowledge (ack) for the address byte. ? send a no acknowledge (nack) for the command and data bytes. ? send all 1s (0xff) as long as the host continues to request data. ? set the cml bit (bit 1) in the status_byte register. ? set the other bit (bit 1) in the status_cml register. ? notify the host through smbalrt , if enabled. invalid or unsupported command code (item 10.9.2) if an invalid or unsupported command code is sent to the pmbus slave, the code is considered to be a data content fault, and the pmbus slave responds as follows: ? send a no acknowledge (nack) for the illegal/ unsupported command byte and data bytes. ? flush and ignore the received command and data. ? set the cml bit (bit 1) in the status_byte register. ? set the invalid/unsupported command bit (bit 7) in the status_cml register. ? notify the host through smbalrt , if enabled. invalid or unsupported data (item 10.9.3) if invalid or unsupported data is sent to the pmbus slave (for certain commands), the pmbus slave considers this to be a data content fault and responds as follows: ? send an acknowledge (ack) for the unsupported data bytes (cannot send a no acknowledge (nack) for the data because the decoding happens only after the data is acknowledged and sent to the decoding unit). ? flush and ignore the received command and data. ? set the cml bit (bit 1) in the status_byte register. ? set the invalid/unsupported data received bit (bit 6) in the status_cml register. ? notify the host through smbalrt , if enabled. data out of range fault (item 10.9.4) data sent to the pmbus slave that is out of range is treated as a data content fault. see the invalid or unsupported data (item 10.9.3) section for the actions taken by the pmbus device. reserved bits (item 10.9.5) accesses to reserved bits are not a fault. writes to reserved bits are ignored, and reads from reserved bits return 0s. write to read-only commands if a host performs a write to a read-only command, the pmbus slave considers this a data content fault and responds as follows: ? send a no acknowledge (nack) for all unexpected data bytes as they are received. ? flush and ignore the received command and data. ? set the cml bit (bit 1) in the status_byte register. ? set the invalid/unsupported data received bit (bit 6) in the status_cml register. ? notify the host through smbalrt , if enabled. note that this is the same error described in the host sends too many bytes (item 10.8.5) section. read from write-only commands if a host performs a read from a write-only command, the pmbus slave considers this a data content fault and responds as follows: ? send all 1s (0xff) as long as the host continues to request data. ? set the cml bit (bit 1) in the status_byte register. ? set the other bit (bit 1) in the status_cml register. note that this is the same error described in the host reads too many bytes (item 10.8.6) section. data sheet adp1055 rev. a | page 53 of 140 layout guidelines this section describes best practices to ensure optimal performance of the adp1055 . in general, place all components as close to the adp1055 as possible. all signals should be referenced to their respective grounds. cs2+ and cs2? pins route the traces from the sense resistor to the adp1055 parallel to each other. keep the traces close together and as far from the switch nodes as possible. vs+ and vs? pins route the traces from the remote voltage sense point to the adp1055 parallel to each other. keep the traces close together and as far from the switch nodes as possible. place a 100 nf capacitor from vs? to agnd to reduce common-mode noise. vdd pin place decoupling capacitors as close to the device as possible. a 4.7 f capacitor from vdd to agnd is recommended. sda and scl pins route the traces to the sda and scl pins parallel to each other. keep the traces close together and as far from the switch nodes as possible. it may be advantageous to add a filtering circuit, as shown in figure 81. figure 81. i 2 c filtering circuit cs1 pin route the traces from the current sense transformer to the adp1055 parallel to each other. keep the traces close together and as far from the switch nodes as possible. exposed pad solder the exposed thermal pad on the underside of the adp1055 package to the pcb agnd plane. vcore pin place a 330 nf decoupling capacitor from the vcore pin to dgnd, as close to the device as possible. res pin place a 10 k, 0.1% resistor from the res pin to agnd, as close to the device as possible. jtd and jrtn pins route a single trace to the adp1055 from the junction diode using a trace to jrtn. if single-ended sensing is preferred, tie the return to agnd using a dedicated trace. make sure to lay out the temperature sensor by isolating it and keeping it away from any direct switch nodes. it is recommended that a 220 nf to 470 nf capacitor be placed between the base-emitter junctions of the thermal sensor. ovp pin route the ovp traces away from any switching nodes to avoid spuriously tripping the comparator at that pin. sync pin it is important to route the trace to the sync pin to prevent any noise from being coupled to the information in the signal. it is recommended that this trace be kept away from switch nodes and routed as an internal layer so that the agnd plane acts as a shield to this trace. agnd and dgnd create an agnd ground plane (preferably in the inner layer) and make a single-point (star) connection to the power supply system ground. connect dgnd to agnd with a very short trace using a star connection. it may be advantageous to have an entire vdd plane as an additional layer for noise immunity. 12004-076 1 j26 hdr1x 2 3 4 +5v scl r55 100 ? d48 1n4148 r56 100 ? c63 33pf c60 33pf 1 2 d41 1n4148 1 2 d50 1n4148 1 2 d43 1n4148 1 2 c61 33pf c62 33pf sda agnd adp1055 data sheet rev. a | page 54 of 140 eeprom the adp1055 has a built-in eeprom controller that is used to communicate with the embedded 8k 8-byte eeprom. the eeprom, also called flash?/ee, is partitioned into two major blocks: the info block and the main block. the info block contains 128 8-bit bytes (for internal use only), and the main block contains 8k 8-bit bytes. the main block is further partitioned into 16 pages; each page contains 512 bytes. overview the eeprom controller provides an interface between the adp1055 core logic and the built-in flash/ee. the user can control data access to and from the eeprom through this controller interface. different i 2 c commands are available for the different operations to the eeprom. communication is initiated by the master device sending a command to the i 2 c slave device to access data from or send data to the eeprom. using read and write commands, data is transferred between devices in a byte wide format. using a read command, data is received from the eeprom and transmitted to the master device. using a write command, data is received from the master device and stored in the eeprom through the eeprom controller. send commands are also supported; a send command is executed by the slave device upon receiving the stop bit. the stop bit is the last bit in a complete data transfer, as defined in the i 2 c communication protocol. for a complete description of the i 2 c protocol, see the philips i 2 c bus specification , version 2.1, dated january 2000. page erase operation the main block consists of 16 equivalent pages of 512 bytes each, numbered page 0 to page 15. page 0 and page 1 of the main block are reserved for storing the default settings and user settings, respectively. page 2 and page 3 are reserved for storing the black box information, and page 4 and page 5 are used to store the gui settings and factory tracking information. the user cannot perform a page erase operation to any of page 0 to page 5. only page 6 to page 15 of the main block can be used to store data. to erase any page from page 6 to page 15, the eeprom must first be unlocked for access. for instructions on how to unlock the eeprom, see the unlock the eeprom section. page 6 to page 15 of the main block can be individually erased using the eeprom_page_erase command (register 0xd4). for example, to perform a page erase of page 10, execute the following command: figure 82. example erase command in this example, command code = 0xd4 and data byte = 0x0a. wait at least 35 ms for the page erase operation to complete before executing the next i 2 c command. the eeprom allows erasing of whole pages only; therefore, to change the data of any single byte in a page, the entire page must first be erased (set high) for that byte to be writable. subsequent writes to any bytes in that page are allowed as long as that byte has not been written to a logic low previously. read operation (byte read and block read) read from main block, page 0 to page 5 page 0 and page 1 of the main block are reserved for storing the default settings and user settings, respectively. page 2 and page 3 are reserved for storing the black box information, and page 4 and page 5 are used to store the gui settings and factory tracking information. these pages are intended to prevent third- party access to this data. to read a page from page 0 to page 5, the user must first unlock the eeprom (see the unlock the eeprom section). after the eeprom is unlocked, page 0 to page 5 are readable using the eeprom_page_xx commands, as described in the read from main block, page 6 to page 15 section. note that when the eeprom is locked, a read from page 0 to page 5 returns invalid data. read from main block, page 6 to page 15 data in page 6 to page 15 of the main block is always readable, even with the eeprom locked. the data in the eeprom main block can be read one byte at a time or in multiple bytes in series using the eeprom_page_xx commands (register 0xb0 to register 0xbf). before executing this command, the user must program the number of bytes to read using the eeprom_num_rd_bytes command (register 0xd2). the user can also program the offset from the page boundary where the first read byte is returned using the eeprom_addr_offset command (register 0xd3). in the following example, three bytes from page 6 are read from the eeprom, starting from the fifth byte of that page. 1. set the number of return bytes = 3. 2. set address offset = 5. 12004-077 s 7-bit slave address w a a p data byte command code a = master-to-slave = slave-to-master 12004-078 s 7-bit slave address w a a p 0xd2 0x03 a = master-to-slave = slave-to-master 12004-079 s 7-bit slave address w a a a a p 0xd3 0x00 0x05 = master-to-slave = slave-to-master data sheet adp1055 rev. a | page 55 of 140 3. read three bytes from page 6. note that the block read command can read a maximum of 255 bytes for any single transaction. write operation (byte write and block write) write to main block, page 0 and page 5 page 0 and page 1 of the main block are reserved for storing the default settings and user settings, respectively. page 2 through page 5 of the main block are reserved for storing the black box information, gui settings, and factory tracking information. the user cannot perform a direct write operation to any page from page 0 to page 5 using the eeprom_page_00 to eeprom_ page_05 commands. a user write to these pages returns a no acknowledge. to program the register contents of page 1 of the main block, it is recommended that the store_user_all command be used (register 0x15). see the save register settings to user settings section. write to main block, page 6 to page 15 before performing a write to page 6 through page 15 of the main block, the user must first unlock the eeprom (see the unlock the eeprom section). data in page 6 to page 15 of the eeprom main block can be programmed (written to) one byte at a time or in multiple bytes in series using the eeprom_page_xx commands (register 0xb6 to register 0xbf). before executing this command, the user can program the offset from the page boundary where the first byte is written using the eeprom_addr_offset command (register 0xd3). if the targeted page has not yet been erased, the user can erase the page as described in the page erase operation section. in the following example, four bytes are written to page 9, starting from the 256 th byte of that page. 1. set address offset = 256. 2. write four bytes to page 9. note that the block write command can write a maximum of 255 bytes for any single transaction. eeprom password on power-up, the eeprom is locked and protected from accidental writes or erases. only reads from page 6 to page 15 of the main block are allowed when the eeprom is locked. before any data can be written (programmed) to the eeprom, the eeprom must be unlocked for write access. after it is unlocked, the eeprom is opened for reading, writing, and erasing. unlock the eeprom to unlock the eeprom, perform two consecutive writes with the correct password (default = 0xff) using the eeprom_ password command (register 0xd5). the eeprom_ unlocked flag (register 0xfe93, bit 15) is set to indicate that the eeprom is unlocked for write access. lock the eeprom to lock the eeprom, write any byte other than the correct password using the eeprom_password command (register 0xd5). the eeprom_unlocked flag (register 0xfe93, bit 15) is cleared to indicate that the eeprom is locked from write access. change the eeprom password to change the eeprom password, follow these steps: 1. enter the correct 32-bit key code using the key_code command (register 0xd7). 2. write the old password using the eeprom_password command (register 0xd5). 3. immediately write the new password using the eeprom_ password command (register 0xd5). the password is now changed to the new password. save the new password to the user settings by executing the store_user_all command (register 0x15). 12004-080 s 7-bit slave address 7-bit slave address w a a r a 0xb6 sr byte count = 0x03 data byte 3 a a na p data byte 1 ... = master-to-slave = slave-to-master 12004-081 s 7-bit slave address w a a 0x00 aa p 0xd3 0x01 = master-to-slave = slave-to-master 12004-082 s 7-bit slave address byte count = 4 w a a a 0xb9 data byte 1 data byte 4 a a p ... = master-to-slave = slave-to-master adp1055 data sheet rev. a | page 56 of 140 downloading eeprom settings to internal registers download user settings to registers the user settings are stored in page 1 of the eeprom main block. these settings are downloaded from the eeprom into the registers under the following conditions: ? on power-up. the user settings are automatically down- loaded into the internal registers, powering the adp1055 up in a state previously saved by the user. ? on execution of the restore_user_all command (register 0x16). this command allows the user to force a download of the user settings from page 1 of the eeprom main block into the internal registers. download factory default settings to registers the factory default settings are stored in page 0 of the eeprom main block. the factory default settings can be downloaded from the eeprom into the internal registers using the restore_ default_all command (register 0x12). note that when this command is executed, the key code and eeprom passwords are also reset to their default factory settings of 0xffffffff and 0xff, respectively. saving register settings to the eeprom the register settings cannot be saved to the factory default set- tings located in page 0 of the eeprom main block. this is to prevent the user from accidentally overriding the factory trim settings and default register settings. save register settings to user settings the register settings can be saved to the user settings located in page 1 of the eeprom main block using the store_user_all command (register 0x15). before this command can be executed, the eeprom must first be unlocked for writing (see the unlock the eeprom section). after the register settings are saved to the user settings, any subsequent power cycle automatically downloads the latest stored user information from the eeprom into the internal registers. note that execution of the store_user_all command auto- matically performs a page erase to page 1 of the eeprom main block, after which the register settings are stored in the eeprom. therefore, it is important to wait at least 35 ms for the operation to complete before executing the next i 2 c command. eeprom crc checksum as a simple method of checking that the values downloaded from the eeprom are consistent with the internal registers, a crc checksum is implemented. ? when the data from the internal registers is saved to the eeprom (page 1 of the main block), the total number of 1s from all the registers is counted and written into the eeprom as the last byte of information. this is called the crc checksum. ? when the data is downloaded from the eeprom into the internal registers, a similar counter that sums all 1s from the values loaded into the registers is saved. this value is compared with the crc checksum from the previous upload operation. if the values match, the download operation was successful. if the values differ, the eeprom download operation failed, and the eeprom crc fault flag is set (bit 4 of register 0x7e). to read the eeprom crc checksum value, execute the eeprom_crc_chksum command (register 0xd1). this command returns the crc checksum accumulated in the counter during the download operation. note that the crc checksum is an 8-bit cyclical accumulator that wraps around to 0 when 255 is reached. data sheet adp1055 rev. a | page 57 of 140 software gui a free software gui is available for programming and configuring the adp1055 . the gui is designed to be intuitive to power supply designers and dramatically reduces power supply design and development time. the software includes filter design and power supply pwm topology windows. the gui is also an information center, displaying the status of all readings, monitoring, and flags on the adp1055 . the gui takes into account all pmbus conversions; the user need only enter the voltage and current settings (or thresholds) in volts and amperes. all pmbus flags and readings are also displayed in the gui. for more information about the gui, see the adp1055 product page). evaluation boards are also available; for more information, see the adp1055 product page). figure 83. voltage settings window of the adp1055 gui figure 84. monitor window of the adp1055 gui 12004-083 12004-084 adp1055 data sheet rev. a | page 58 of 140 standard pmbus commands supported by the adp1055 table 12 lists the standard pmbus commands that are implemented on the adp1055 . many of these commands are implemented in registers, which share the same hexadecimal value as the pmbus command code. all commands are maskable with the exceptions note d in table 12. table 12. pmbus command list command code command name 0x01 operation 0x02 on_off_config 0x03 clear_faults 0x10 write_protect 0x12 restore_default_all 0x15 store_user_all 1 0x16 restore_user_all 1 0x19 capability 0x1b smbalert_mask 0x20 vout_mode 0x21 vout_command 0x22 vout_trim 0x23 vout_cal_offset 0x24 vout_max 0x27 vout_transition_rate 0x28 vout_droop 0x29 vout_scale_loop 0x2a vout_scale_monitor 0x33 frequency_switch 0x35 vin_on 0x36 vin_off 0x37 interleave 0x38 iout_cal_gain 0x39 iout_cal_offset 0x40 vout_ov_fault_limit 0x41 vout_ov_fault_response 0x42 vout_ov_warn_limit 0x43 vout_uv_warn_limit 0x44 vout_uv_fault_limit 0x45 vout_uv_fault_response 0x46 iout_oc_fault_limit 0x47 iout_oc_fault_response 0x48 iout_oc_lv_fault_limit 0x49 iout_oc_lv_fault_response 0x4a iout_oc_warn_limit 0x4b iout_uc_fault_limit 0x4c iout_uc_fault_response 0x4f ot_fault_limit 0x50 ot_fault_response 0x51 ot_warn_limit 0x55 vin_ov_fault_limit 0x56 vin_ov_fault_response 0x59 vin_uv_fault_limit 0x5a vin_uv_fault_response 0x5b iin_oc_fault_limit 0x5c iin_oc_fault_response 0x5e power_good_on command code command name 0x5f power_good_off 0x60 ton_delay 0x61 ton_rise 0x62 ton_max_fault_limit 0x63 ton_max_fault_response 0x64 toff_delay 0x65 toff_fall 0x66 toff_max_warn_limit 0x68 pout_op_fault_limit 0x69 pout_op_fault_response 0x78 status_byte 0x79 status_word 0x7a status_vout 0x7b status_iout 0x7c status_input 0x7d status_temperature 0x7e status_cml 0x7f status_other 0x80 status_mfr_specific 0x88 read_vin 0x89 read_iin 0x8b read_vout 0x8c read_iout 0x8d reserved 0x8e read_temperature_2 0x8f read_temperature_3 0x94 read_duty_cycle 0x95 read_frequency 0x96 read_pout 0x98 pmbus_revision 0x99 mfr_id 0x9a mfr_model 0x9b mfr_revision 0x9c mfr_location 0x9d mfr_date 0x9e mfr_serial 0xad ic_device_id 0xae ic_device_rev 0xb0 eeprom_page_00 0xb1 eeprom_page_01 0xb2 eeprom_page_02 0xb3 eeprom_page_03 0xb4 eeprom_page_04 0xb5 eeprom_page_05 0xb6 eeprom_page_06 0xb7 eeprom_page_07 0xb8 eeprom_page_08 data sheet adp1055 rev. a | page 59 of 140 command code command name 0xb9 eeprom_page_09 0xba eeprom_page_10 0xbb eeprom_page_11 0xbc eeprom_page_12 0xbd eeprom_page_13 0xbe eeprom_page_14 0xbf eeprom_page_15 0xd0 slv_addr_select 1 0xd1 eeprom_crc_chksum 0xd2 eeprom_num_rd_bytes command code command name 0xd3 eeprom_addr_offset 0xd4 eeprom_page_erase 0xd5 eeprom_password 1 0xd6 trim_password 0xd7 key_code 1 0xf1 eeprom_info 1 0xf2 read_blackbox_curr 0xf3 read_blackbox_prev 0xf4 cmd_mask 1 0xf5 extcmd_mask 1 1 this command is not maskable. adp1055 data sheet rev. a | page 60 of 140 manufacturer specific commands table 13 lists the manufacturer-specific pmbus commands that are implemented on the adp1055 . these commands are implemented in registers, which share the same hexadecimal value as the pmbus command code. all commands are maskable. table 13. manufacturer specific command list command code command name 0xfe00 go_cmd 0xfe01 nm_digfilt_lf_gain_setting 0xfe02 nm_digfilt_zero_setting 0xfe03 nm_digfilt_pole_setting 0xfe04 nm_digfilt_hf_gain_setting 0xfe05 llm_digfilt_lf_gain_setting 0xfe06 llm_digfilt_zero_setting 0xfe07 llm_digfilt_pole_setting 0xfe08 llm_digfilt_hf_gain_setting 0xfe09 ss_digfilt_lf_gain_setting 0xfe0a ss_digfilt_zero_setting 0xfe0b ss_digfilt_pole_setting 0xfe0c ss_digfilt_hf_gain_setting 0xfe0d outa_redge_setting 0xfe0e outa_fedge_setting 0xfe0f outb_redge_setting 0xfe10 outb_fedge_setting 0xfe11 outc_redge_setting 0xfe12 outc_fedge_setting 0xfe13 outd_redge_setting 0xfe14 outd_fedge_setting 0xfe15 sr1_redge_setting 0xfe16 sr1_fedge_setting 0xfe17 sr2_redge_setting 0xfe18 sr2_fedge_setting 0xfe19 sr1_redge_llm_setting 0xfe1a sr1_fedge_llm_setting 0xfe1b sr2_redge_llm_setting 0xfe1c sr2_fedge_llm_setting 0xfe1d adt_config 0xfe1e adt_threshold 0xfe1f outa_dead_time 0xfe20 outb_dead_time 0xfe21 outc_dead_time 0xfe22 outd_dead_time 0xfe23 sr1_dead_time 0xfe24 sr2_dead_time 0xfe25 vsbal_setting 0xfe26 vsbal_outa_b 0xfe27 vsbal_outc_d 0xfe28 vsbal_sr1_2 0xfe29 ffwd_setting 0xfe2a ishare_setting 0xfe2b ishare_bandwidth 0xfe2c iin_oc_fast_setting 0xfe2d iout_oc_fast_setting 0xfe2e iout_uc_fast_setting 0xfe2f vout_ov_fast_setting command code command name 0xfe30 debounce_setting_1 0xfe31 debounce_setting_2 0xfe32 debounce_setting_3 0xfe33 debounce_setting_4 0xfe34 vout_ov_fast_fault_response 0xfe35 iout_oc_fast_fault_response 0xfe36 iout_uc_fast_fault_response 0xfe37 iin_oc_fast_fault_response 0xfe38 ishare_fault_response 0xfe39 gpio1_fault_response 0xfe3a gpio2_fault_response 0xfe3b gpio3_fault_response 0xfe3c gpio4_fault_response 0xfe3d pwm_fault_mask 0xfe3e delay_time_unit 0xfe3f wdt_setting 0xfe40 gpio_setting 0xfe41 gpio1_2_karnaugh_map 0xfe42 gpio3_4_karnaugh_map 0xfe43 pgood_fault_deb 0xfe44 pgood1_fault_select 0xfe45 pgood2_fault_select 0xfe46 soft_start_blanking 0xfe47 soft_stop_blanking 0xfe48 blackbox_setting 0xfe49 pwm_disable_setting 0xfe4a filter_transition 0xfe4b deep_llm_setting 0xfe4c deep_llm_disable_setting 0xfe4d ovp_fault_config 0xfe4e cs1_setting 0xfe4f cs2_setting 0xfe50 pulse_skip_and_shutdown 0xfe51 soft_start_setting 0xfe52 sr_delay 0xfe53 modulation_limit 0xfe55 sync 0xfe56 duty_bal_edgesel 0xfe57 double_upd_rate 0xfe58 vin_scale_monitor 0xfe59 iin_cal_gain 0xfe5a tsns_setting 0xfe5b auto_go_cmd 0xfe5c diode_emulation 0xfe5d cs2_const_cur_mode 0xfe5e nl_err_gain_factor 0xfe5f sr_setting 0xfe60 nominal_temp_pole data sheet adp1055 rev. a | page 61 of 140 command code command name 0xfe61 low_temp_pole 0xfe62 low_temp_setting 0xfe63 gpio3_4_snubber_on_time 0xfe64 gpio3_4_snubber_delay 0xfe65 vout_droop_setting 0xfe66 nl_burst_mode 0xfe67 hf_adc_config 0xfe80 vs_trim 0xfe81 vff_gain_trim 0xfe82 cs1_gain_trim 0xfe86 tsns_extfwd_gain_trim 0xfe87 tsns_extfwd_offset_trim 0xfe88 tsns_extrev_gain_trim 0xfe89 tsns_extrev_offset_trim 0xfe8c fault_vout 0xfe8d fault_iout 0xfe8e fault_input 0xfe8f fault_temperature command code command name 0xfe90 fault_cml 0xfe91 fault_other 0xfe92 fault_mfr_specific 0xfe93 fault_unknown 0xfe94 status_unknown 0xfe95 first_fault_id 0xfe96 vff_value 0xfe97 vs_value 0xfe98 cs1_value 0xfe99 cs2_value 0xfe9a pout_value 0xfe9b reserved 0xfe9c tsns_extfwd_value 0xfe9d tsns_extrev_value 0xfe9f modulation_value 0xfea0 ishare_value 0xfea3 add_adc_value adp1055 data sheet rev. a | page 62 of 140 standard pmbus command descriptions standard pmbus commands operation the operation command, in conjunction with the ctrl pin, is us ed to turn the device on and off. illegal values are 11xxxxxx. table 14. register 0x01operation bits bit name r/w description [7:6] enable r/w these bits determine the device response to the operation command. 00 = immediate off (no sequencing). 01 = soft off (power down according to the programmed toff_delay and toff_fall). 10 = device on. 11 = reserved. [5:0] reserved r reserved. on_off_config the on_off_config command configures the combination of the ctrl pin input and the operation command needed to turn the device on and off, including how the device responds when power is applied. illegal values are xxx100xx. table 15. register 0x02on_off_config bits bit name r/w description [7:5] reserved r reserved. 4 power-up control r/w sets the device power-up response. 0 = device powers up when power is present. 1 = device powers up only when commanded by the ctrl pin and the operation command. 3 command enable r/w controls how the device res ponds to the operation command. 0 = ignores operation command. 1 = the operation command must be set to 1 to enable the device (in addition to setting bit 2). 2 pin enable r/w controls how the device responds to the value of the ctrl pin. 0 = ignores the ctrl pin. 1 = ctrl pin must be asserted to enable the device (in addition to setting bit 3). 1 ctrl pin polarity r/w sets the polarity of the ctrl pin. 0 = active low. 1 = active high. 0 ctrl pin power- down action r/w actions to take on power-down when power-down is activated by the ctrl pin. 0 = uses the toff_delay and toff_fall values to stop the transfer of energy to the output. 1 = turns off the output and stops energy tran sfer to the output as quickly as possible. clear_faults the clear_faults command is a send byte, no data. this command clears all fault bits in all pmbus status registers simultaneous ly. table 16. register 0x03clear_faults bits bit name type description n/a clear_faults send clears all bits in the pmbus status registers (register 0x78 to register 0x7e) simultaneously. write_protect the write_protect command is used to protect the pmbus device against accidental writes. reads to the device are allowed regardless of the setting of this command. table 17. register 0x10write_protect bits bit name r/w description 7 write protect 1 r/w setting this bit disables writes to all commands except write_protect. 6 write protect 2 r/w setting this bit disables writes to all commands except write_protect, operation, and page. 5 write protect 3 r/w setting this bit disables writes to all comma nds except write_protect, operation, page, on_off_config, and vout_command. [4:0] reserved r reserved. data sheet adp1055 rev. a | page 63 of 140 restore_default_all table 18. register 0x12restore_default_all bits bit name type description n/a restore_default_all send this command downloads the factory defaul t settings from the eeprom into operating memory. it also resets the eeprom password and the key code to their default values. store_user_all table 19. register 0x15store_user_all bits bit name type description n/a store_user_all send this command copies the entire contents of operating memory into the eeprom (page 1 of the main block) as the user settings. restore_user_all table 20. register 0x16restore_user_all bits bit name type description n/a restore_user_all send this command downloads the st ored user settings from eeprom into operating memory. capability this command allows host systems to determine the capabilities of the pmbus device (default value is 0xb0). table 21. register 0x19capability bits bit name r/w description 7 packet error checking r checks packet error capability of the device. 1 = supported. [6:5] maximum bus speed r checks the pmbus speed capability of the device. 01 = maximum bus speed is 400 khz. 4 smbalrt r checks support for the smbalrt pin and the smbus alert response address protocol. 1 = supported. [3:0] reserved r reserved. smbalert_mask table 22. register 0x1bsmbalert_mask bits bit name r/w description [15:8] status_x command code w command code of the status_x mask register to update. [7:0] mask byte w update mask register with this value. vout_mode the vout_mode command sets the data format for output voltage related data. the data byte for the vout_mode command consists of a 3-bit mode and 5-bit exponent parameter. the 3-bit mode determines whether the device uses linear format or direct format for the output voltage related commands. the 5-bit parameter sets the exponent value for linear format. vout_mode[7:5] must be equal to 000. table 23. register 0x20vout_mode bits bit name r/w description [7:5] mode r returns the output voltage data format. the value is fixed at 000, which means that only linear data format is supported. [4:0] exponent-n r/w twos complement n exponent used in the output voltage related commands in linear data format (v = y 2 n ). vout_command the vout_command command sets the output voltage. exponent n is set using vout_mode[4:0]. bits[7:5] must be equal to 000. table 24. register 0x21vout_command (require s use of the go bit in register 0xfe00) bits bit name r/w description [15:0] mantissa-y r/w 16-bit unsigned integer y value for linear data format (v = y 2 n ). n is defined using vout_mode[4:0]. adp1055 data sheet rev. a | page 64 of 140 vout_trim the vout_trim command applies a fixed offset voltage to the vout_command value. table 25. register 0x22vout_trim bits bit name r/w description [15:0] offset trim r/w twos complement integer used to apply a fixed offset voltage to the vout_command value. vout_cal_offset the vout_cal_offset command is used to apply a fixed offset voltage to the vout_command value. table 26. register 0x23vout_cal_offset bits bit name r/w description [15:0] offset trim r/w twos complement integer used to apply a fixed offset voltage to the vout_command value. vout_max the vout_max command sets an upper limit on the output voltage. exponent n is set using vout_mode[4:0]. table 27. register 0x24vout_max bits bit name r/w description [15:0] mantissa-y r/w sets the output voltage upper limit. 16-bit unsigned integer y value for linear data format (v = y 2 n ). vout_transition_rate when the device receives a vout_command or operation command that causes the output voltage to change, this command sets the output transition rate (or slew rate), in mv/s, at which the vs pins change voltage. table 28. register 0x27vout_transition_rate bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). vout_droop the vout_droop command sets the rate, in mv/a, at which the output voltage decreases (or increases) with increasing (or decreasing) output current. table 29. register 0x28vout_droop bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). vout_scale_loop the vout_scale_loop command sets the gain (k r ) by which the commanded voltage (v out ) is scaled to generate the internal reference voltage (v ref ). v ref = v out k r , where k r = y 2 n . table 30. register 0x29vout_scale_loop bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). vout_scale_monitor the vout_scale_monitor command sets the gain (k vout ) by which the sensed output voltage at the dut (v out_dut ) is scaled to generate the reading for the read_vout command. read_vout = v out_dut k vout , where k vout = y 2 n . table 31. register 0x2avout_scale_monitor bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). data sheet adp1055 rev. a | page 65 of 140 frequency_switch the frequency_switch command sets the switching frequency (in khz) for the pmbus device. for a list of all supported switching frequencies, see table 244. table 32. register 0x33frequency_switch (requi res use of the go bit in register 0xfe00) bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). vin_on the vin_on command sets the value of the input voltage (v rms) at which the device starts power conversion. setting vin_on = 0 effectively disables this function. table 33. register 0x35vin_on bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). vin_off the vin_off command sets the value of the input voltage (v rms) at which the device stops power conversion. vin_off is not chec ked until the device reaches the regulation voltage or ton_max has expired. table 34. register 0x36vin_off bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). interleave the interleave command is used to arrange multiple devices so that their switching periods can be distributed in time. table 35. register 0x37interleave bits bit name r/w description [15:12] reserved r reserved. [11:8] group id number r/w group identification number. [7:4] number in group r/w number of units in the group. [3:0] interleave order r/w interleave order for this unit. 0000 = 0 22.5 (0 t sw /16). 0001 = 1 22.5 (1 t sw /16). 0010 = 2 22.5 (2 t sw /16). 0011 = 3 22.5 (3 t sw /16). 1111 = 15 22.5 (15 t sw /16). iout_cal_gain the iout_cal_gain command sets the ratio of the voltage at the current sense pins to the sensed current (in m). table 36. register 0x38iout_cal_gain bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). adp1055 data sheet rev. a | page 66 of 140 iout_cal_offset the iout_cal_offset command is used to null any offsets in the output current sensing circuit (in amperes). table 37. register 0x39iout_cal_offset bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). vout_ov_fault_limit the vout_ov_fault_limit command sets the upper voltage threshold (in volts) measured at the sense/output pin that causes an overvoltage fault condition. the exponent n is set using vout_mode[4:0]. table 38. register 0x40vout_ov_fault_limit bits bit name r/w description [15:0] mantissa-y r/w unsigned y-mantissa used in output voltage related commands in linear data format (v = y 2 n ). vout_ov_fault_response the vout_ov_fault_response command instructs the device on the actions to take due to an output overvoltage fault. the device notifies the host and sets the vout_ov_fault bit in the status_byte register, the vout bit in the status_word register, and the vout_ov_fault bit in the status_vout register. table 39. register 0x41vout_ov_fault_response bits bit name r/w description [7:6] response r/w determines the device response to an overvoltage fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the delay time (bits[2:0]). if the fault persists, retry the number of times specified by bits[5:3]. 1 0 shut down, disable the output, and re spond as programmed in the retry setting (bits[5:3]). 1 1 disable the output while th e fault is present. operation resumes and the output is enabled when the faul t condition no longer exists. [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay time r/w number of delay time units (see register 0xfe3e). vout_ov_warn_limit the vout_ov_warn_limit command sets the upper voltage threshold (in volts) measured at the sense/output pin that causes an overvoltage warning condition. the exponent n is set using vout_mode[4:0]. the device notifies the host and sets the none_of_th e_ above bit in the status_byte register, the vout bit in the status_word register, and the vout_ov_warning bit in the status_vout register. table 40. register 0x42vout_ov_warn_limit bits bit name r/w description [15:0] mantissa-y r/w unsigned y-mantissa used in output voltage related commands in linear data format (v = y 2 n ). data sheet adp1055 rev. a | page 67 of 140 vout_uv_warn_limit the vout_uv_warn_limit command sets the lower voltage threshold (in volts) measured at the sense/output pin that causes an undervoltage warning condition. the exponent n is set using vout_mode[4:0]. the device notifies the host and sets the none_of_ the_above bit in the status_byte register, the vout bit in the status_word register, and the vout_uv_warning bit in the status_vout register. table 41. register 0x43vout_uv_warn_limit bits bit name r/w description [15:0] mantissa-y r/w unsigned y-mantissa used in output voltage related commands in linear data format (v = y 2 n ). vout_uv_fault_limit the vout_uv_fault_limit command sets the threshold value (in volts) measured at the sense/output pin that causes an under- voltage fault condition. the exponent n is set using vout_mode[4:0]. table 42. register 0x44vout_uv_fault_limit bits bit name r/w description [15:0] mantissa-y r/w unsigned y-mantissa used in output voltage related commands in linear data format (v = y 2 n ). vout_uv_fault_response the vout_uv_fault_response command instructs the device on actions to take due to an output undervoltage fault condition. the device notifies the host and sets the none_of_the_above bit in the status_byte register, the vout bit in the status_word register, and the vout_uv_fault bit in the status_vout register. table 43. register 0x45vout_uv_fault_response bits bit name r/w description [7:6] response r/w determines the device res ponse to an undervolta ge fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the delay time (bits[2:0]). if the fault persists, retry the number of times specified by bits[5:3]. 1 0 shut down, disable the output, and re spond as programmed in the retry setting (bits[5:3]). 1 1 disable the output while th e fault is present. operation resumes and the output is enabled when the faul t condition no longer exists. [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w number of delay time units (see register 0xfe3e). adp1055 data sheet rev. a | page 68 of 140 iout_oc_fault_limit the iout_oc_fault_limit command sets the threshold value (in amperes) measured at the sense pins that causes an overcurrent fault condition. table 44. register 0x46iout_oc_fault_limit bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). iout_oc_fault_response the iout_oc_fault_response command instructs the device on actions to take due to an output overcurrent fault condition. the device notifies the host and sets the iout_oc_fault bit in the status_byte register, the iout bit in the status_word register, and the iout_oc_fault bit in the status_iout register. table 45. register 0x47iout_oc_fault_response bits bit name r/w description [7:6] response r/w determines the device response to an overcurrent fault condition. bit 7 bit 6 response 0 0 operate in current limiting mode, maintaining the output current at iout_oc_fault_limit. 0 1 operate in current limiting mode, maintaining the output current at iout_oc_fault_limit. if v out falls below the iout_oc_lv_fault_limit, respond as programmed by the retry setting (bits[5:3]). 1 0 continue operation in current limiting mode for the delay time (bits[2:0]). if the device is still in current limiting mode , respond as programmed by the retry setting (bits[5:3]). 1 1 shut down, disable the output, and re spond as programmed by the retry setting (bits[5:3]). [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w number of delay time units (see register 0xfe3e). iout_oc_lv_fault_limit the iout_oc_lv_fault_limit command sets the lower voltage threshold (in volts) measured at the sense/output pin that causes an undervoltage-in-clm fault condition. this limit applies only when the device is operating in current limiting mode (clm). table 46. register 0x48iout_oc_lv_fault_limit bits bit name r/w description [15:0] mantissa-y r/w unsigned y-mantissa used in output voltage related commands in linear data format (v = y 2 n ). n is specified by vout_mode[4:0]. data sheet adp1055 rev. a | page 69 of 140 iout_oc_lv_fault_response the iout_oc_lv_fault_response command instructs the device on actions to take due to an output undervoltage-in-clm fault condition. the device notifies the host and sets the iout_oc_fault bit in the status_byte register, the iout bit in the status_ word register, and the iout_oc_lv_fault bit in the status_iout register. table 47. register 0x49iout_oc_lv_fault_response bits bit name r/w description [7:6] response r/w determines the device respon se to an undervoltage-in-clm fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the delay time (bits[2:0]). if the fault persists, retry the number of times specified by bits[5:3]. 1 0 shut down, disable the output, and re spond as programmed in the retry setting (bits[5:3]). 1 1 disable the output while th e fault is present. operation resumes and the output is enabled when the faul t condition no longer exists. [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w number of delay time units (see register 0xfe3e). iout_oc_warn_limit the iout_oc_warn_limit command sets the current (in amperes) measured at the sense/output pin that causes an overcurrent warning condition. the device notifies the host and sets the none_of_the_above bit in the status_byte register, the iout bit in the status_word register, and the iout_oc_warning bit in the status_iout register. table 48. register 0x4aiout_oc_warn_limit bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). adp1055 data sheet rev. a | page 70 of 140 iout_uc_fault_limit the iout_uc_fault_limit command sets the current (in amperes) measured at the sense/output pin that causes an undercurrent fault condition. table 49. register 0x4biout_uc_fault_limit bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). iout_uc_fault_response the iout_uc_fault_response command instructs the device on actions to take due to an output undercurrent fault condition. the device notifies the host and sets the none_of_the_above bit in the status_byte register, the iout bit in the status_word register, and the iout_uc_fault bit in the status_iout register. table 50. register 0x4ciout_uc_fault_response bits bit name r/w description [7:6] response r/w determines the device res ponse to an undercurrent fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 operate in current limiting mode, maintaining the output current at iout_oc_fault_limit. if v out falls below the iout_oc_lv_fault_limit, respond as programmed by the retry setting (bits[5:3]). 1 0 continue operation in current limiting mode for the delay time (bits[2:0]). if the device is still in current limiting mode , respond as programmed by the retry setting (bits[5:3]). 1 1 shut down, disable the output, and re spond as programmed by the retry setting (bits[5:3]). [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w number of delay time units (see register 0xfe3e). ot_fault_limit the ot_fault_limit command sets the threshold value (in c) that causes an overtemperature fault condition. table 51. register 0x4fot_fault_limit bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). data sheet adp1055 rev. a | page 71 of 140 ot_fault_response the ot_fault_response command instructs the device on actions to take due to an overtemperature fault condition. the device not ifies the host and sets the temperature bit in the status_byte register and the ot_fault bit in the status_temperature register. table 52. register 0x50ot_fault_response bits bit name r/w description [7:6] response r/w determine the device response to an overtemperature fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the delay time (bits[2:0]). if the fault persists, retry the number of times specified by bits[5:3]. 1 0 shut down, disable the output, and re spond as programmed in the retry setting (bits[5:3]). 1 1 disable the output while th e fault is present. operation resumes and the output is enabled when the faul t condition no longer exists. [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w number of delay time units (see register 0xfe3e). ot_warn_limit the ot_warn_limit command sets the threshold value (in c) for an overtemperature warning condition. the device notifies the host and sets the temperature bit in the status_byte register and the ot_warning bit in the status_temperature register. table 53. register 0x51ot_warn_limit bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). vin_ov_fault_limit the vin_ov_fault_limit command sets the upper voltage threshold (in volts) measured at the sense/input pin that causes an overvoltage fault condition. table 54. register 0x55vin_ov_fault_limit bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). adp1055 data sheet rev. a | page 72 of 140 vin_ov_fault_response the vin_ov_fault_response command instructs the device on the actions to take due to an input overvoltage fault condition. the device notifies the host and sets the none_of_the_above bit in the status_byte register, the input bit in the status_word register, and the vin_ov_fault bit in the status_input register. table 55. register 0x56vin_ov_fault_response bits bit name r/w description [7:6] response r/w determines the device respon se to an input overvoltage fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the delay time (bits[2:0]). if the fault persists, retry the number of times specified by bits[5:3]. 1 0 shut down, disable the output, and re spond as programmed in the retry setting (bits[5:3]). 1 1 disable the output while th e fault is present. operation resumes and the output is enabled when the faul t condition no longer exists. [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w number of delay time units (see register 0xfe3e). vin_uv_fault_limit the vin_uv_fault_limit command sets the lower voltage threshold (in volts) measured at the sense/input pin that causes an undervoltage fault condition. table 56. register 0x59vin_uv_fault_limit bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). vin_uv_fault_response the vin_uv_fault_response command instructs the device on the actions to take due to an input undervoltage fault condition. the device notifies the host and sets the vin_uv_fault bit in the status_byte register, the input bit in the status_word register, and the vin_uv_fault bit in the status_input register. table 57. register 0x5avin_uv_fault_response bits bit name r/w description [7:6] response r/w determines the device respon se to an input undervol tage fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the delay time (bits[2:0]). if the fault persists, retry the number of times specified by bits[5:3]. 1 0 shut down, disable the output, and re spond as programmed in the retry setting (bits[5:3]). 1 1 disable the output while th e fault is present. operation resumes and the output is enabled when the faul t condition no longer exists. data sheet adp1055 rev. a | page 73 of 140 bits bit name r/w description [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w number of delay time units (see register 0xfe3e). iin_oc_fault_limit the iin_oc_fault_limit command sets the threshold value (in amperes) measured at the sense/input pin that causes an overcurrent fault condition. table 58. register 0x5biin_oc_fault_limit bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). iin_oc_fault_response the iin_oc_fault_response command instructs the device on actions to take due to an input overcurrent fault condition. the device notifies the host and sets the other bit in the status_byte register, the input bit in the status_word register, and the iin_oc_fault bit in the status_input register. table 59. register 0x5ciin_oc_fault_response bits bit name r/w description [7:6] response r/w determines the device respon se to an input overcurrent fault condition. bit 7 bit 6 response 0 0 operate in current limiting mode, maintaining the output current at iout_oc_fault_limit. 0 1 operate in current limiting mode, maintaining the output current at iout_oc_fault_limit. if v out falls below the iout_oc_lv_fault_limit, respond as programmed by the retry setting (bits[5:3]). 1 0 continue operation in current limiting mode for the delay time (bits[2:0]). if the device is still in current limiting mode , respond as programmed by the retry setting (bits[5:3]). 1 1 shut down, disable the output, and re spond as programmed by the retry setting (bits[5:3]). [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w number of delay time units (see register 0xfe3e). adp1055 data sheet rev. a | page 74 of 140 power_good_on the power_good_on command sets the output voltage (in volts) at which the power_good signal is asserted. table 60. register 0x5epower_good_on bits bit name r/w description [15:0] mantissa-y r/w unsigned y-mantissa used in output voltage related commands in linear data format (v = y 2 n ). power_good_off the power_good_off command sets the output voltage (in volts) at which the power_good signal is deasserted. table 61. register 0x5fpower_good_off bits bit name r/w description [15:0] mantissa-y r/w unsigned y-mantissa used in output voltage related commands in linear data format (v = y 2 n ). ton_delay the ton_delay command sets the turn-on delay time in milliseconds (ms) from start (on_off_config) until v out starts to rise. the range is 0 ms to 1023 ms, in steps of 1 ms. the calculated value is rounded down. table 62. register 0x60ton_delay bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). ton_rise the ton_rise command sets the rise time (in ms) from when v out starts to rise until the voltage enters the regulation band. table 63. register 0x61ton_rise bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). ton_max_fault_limit the ton_max_fault_limit command sets the upper time threshold (in ms) from power-up to the vout_uv_fault limit. table 64. register 0x62ton_max_fault_limit bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). ton_max_fault_response the ton_max_fault_response command instructs the device on the actions to take due to a ton_max fault condition. the device notifies the host and sets the none_of_the_above bit in the status_byte register, the vout bit in the status_word register, and the ton_max_fault bit in the status_vout register. table 65. register 0x63ton_max_fault_response bits bit name r/w description [7:6] response r/w determines the device response to a ton_max fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the delay time (bits[2:0]). if the fault persists, retry the number of times specified by bits[5:3]. 1 0 shut down, disable the output, and re spond as programmed in the retry setting (bits[5:3]). 1 1 disable the output while th e fault is present. operation resumes and the output is enabled when the faul t condition no longer exists. data sheet adp1055 rev. a | page 75 of 140 bits bit name r/w description [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w number of delay time units (see register 0xfe3e). toff_delay the toff_delay command sets the turn-off delay time in millisec onds (ms) from stop (on_off_config) until the device stops transferring energy to the output. the range is 0 ms to 1023 ms, in steps of 1 ms. the calculated value is rounded down. table 66. register 0x64toff_delay bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). toff_fall the toff_fall command sets the fall time (in ms) from the end of the turn-off delay time to voltage = 0 v. table 67. register 0x65toff_fall bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). toff_max_warn_limit the toff_max_warn_limit command sets the upper time threshold (in ms) that causes a toff_max warning condition, that is, the time it takes to power down the output voltage from v out to 12.5% of v out . the device notifies the host and sets the none_of_the_ above bit in the status_byte register, the vout bit in the status_word register, and the toff_max_warning bit in the status_vout register. table 68. register 0x66toff_max_warn_limit bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). pout_op_fault_limit the pout_op_fault_limit command sets the upper power threshold (in watts) measured at the sense/output pin that causes an output overpower fault condition. table 69. register 0x68pout_op_fault_limit bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). adp1055 data sheet rev. a | page 76 of 140 pout_op_fault_response the pout_op_fault_response command instructs the device on the actions to take due to an output overpower fault condition. the device notifies the host and sets the iout_oc_fault bit in the status_byte register, the iout/pout bit in the status_word register, and the pout_op_fault bit in the status_iout register. table 70. register 0x69pout_op_fault_response bits bit name r/w description [7:6] response r/w determines the device response to an overpower fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the delay time (bits[2:0]). if the fault persists, retry the number of times specified by bits[5:3]. 1 0 shut down, disable the output, and re spond as programmed in the retry setting (bits[5:3]). 1 1 disable the output while th e fault is present. operation resumes and the output is enabled when the faul t condition no longer exists. [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w number of delay time units (see register 0xfe3e). status_byte the status_byte register returns the lower byte of the status_word register. a value of 1 in this command indicates that a faul t has occurred. as per the pmbus standard, the busy bit is writable to allow the user to clear that latched bit using a write com mand with a 1 to bit 7, similar to other status_xxx commands. the other bits in this register cannot be cleared with a write to the statu s_byte command, but should be cleared with a write to the status_vout, status_iout, status_input, status_temp, or status_cml command. table 71. register 0x78status_byte bits bit name r/w description 7 busy r/w this bit is asserted if the device is busy and unable to respond. 6 power_off r this bit is asserted if the unit is not providing power to the output. 5 vout_ov_fault r an output ov ervoltage fault has occurred. 4 iout_oc_fault r an output ov ercurrent fault has occurred. 3 vin_uv_fault r an input unde rvoltage fault has occurred. 2 temperature r a temperature fault or warning has occurred. 1 cml r a communications, memory, or logic fault has occurred. 0 none_of_the_above r a fault or warning not listed in bits[7:1] has occurred. data sheet adp1055 rev. a | page 77 of 140 status_word the status_word register returns the upper and lower bytes of the status_word command. a value of 1 in this command indicates that a fault has occurred. table 72. register 0x79status_word bits bit name r/w description 15 vout r output voltage fault or warn ing. a bit in status_vout is set. 14 iout/pout r output current or o utput power fault or warning. a bit in status_iout is set. 13 input r input voltage, input current, or input power fault or warning. a bit in status_input is set. 12 mfr r manufacturer-specific fault or warning. 11 power_good r power_good is a negation of power_good, which me ans that the output power is not good. this bit is set when the sensed v out is less than the limit programmed in the power_good_off command. 10 fans r not supported. 9 other r a bit in status_other is set. 8 unknown r a fault or warning not listed in status_word[15:1]. 7 busy r/w this bit is asserted if the device is busy and unable to respond. 6 power_off r this bit is asserted if the unit is not providing power to the output. 5 vout_ov_fault r an output ov ervoltage fault has occurred. 4 iout_oc_fault r an output ov ercurrent fault has occurred. 3 vin_uv_fault r an input unde rvoltage fault has occurred. 2 temperature r a temperature fault or warning has occurred. 1 cml r a communications, memory, or logic fault has occurred. 0 none_of_the_above r a fault or warning not listed in bits[7:1] has occurred. status_vout the status_vout register returns the status of the output voltage. a value of 1 in this command indicates that a fault has occu rred. table 73. register 0x7astatus_vout bits bit name r/w description 7 vout_ov_fault r/w an output ov ervoltage fault has occurred. 6 vout_ov_warn r/w an output ov ervoltage warning has occurred. 5 vout_uv_warn r/w an output unde rvoltage warning has occurred. 4 vout_uv_fault r/w an output un dervoltage fault has occurred. 3 vout_max_warn r/w an attempt was made to set the output voltage to a value greater than the vout_max command. 2 ton_max_fault r/w the device took too long to po wer up without reaching the vout_uv fault limit. 1 toff_max_warn r/w the device took too long to power down to 12.5% of its output voltage. 0 vout_tracking_err r not supported. status_iout the status_iout register returns the status of the output current. a value of 1 in this command indicates that a fault has occu rred. table 74. register 0x7bstatus_iout bits bit name r/w description 7 iout_oc_fault r/w an output ov ercurrent fault has occurred. 6 iout_oc_lv_fault r/w an output overcurrent fa ult and a low voltage fault have occurred. 5 iout_oc_warn r/w an output over current warning has occurred. 4 iout_uc_fault r/w an output un dercurrent fault has occurred. 3 ishare_fault r/w a current sharing fault has occurred. 2 plim_mode r not supported. 1 pout_op_fault r/w an output overpower fault has occurred. 0 pout_op_warn r not supported. adp1055 data sheet rev. a | page 78 of 140 status_input the status_input register returns the status of the input. a value of 1 in this command indicates that a fault has occurred. table 75. register 0x7cstatus_input bits bit name r/w description 7 vin_ov_fault r/w an input overvoltage fault has occurred. 6 vin_ov_warn r not supported. 5 vin_uv_warn r not supported. 4 vin_uv_fault r/w an input un dervoltage fault has occurred. 3 vin_low r/w the device is off due to insufficient input voltag e; that is, the input voltage is below the turn-off threshold. 2 iin_oc_fault r/w an input overcurrent fault has occurred. 1 iin_oc_warn r not supported. 0 pin_op_warn r not supported. status_temperature the status_temperature register returns temperature status. a value of 1 in this command indicates that a fault has occurred. table 76. register 0x7dstatus_temperature bits bit name r/w description 7 ot_fault r/w an overtemperature fault has occurred. 6 ot_warn r/w an overtemperature warning has occurred. 5 ut_warn r not supported. 4 ut_fault r not supported. [3:0] reserved r reserved. status_cml the status_cml register returns communications, memory, and logic (cml) status. a value of 1 in this command indicates that a fault has occurred. table 77. register 0x7estatus_cml bits bit name r/w description 7 cmd_err r/w invalid or unsupported command received. 6 data_err r/w invalid or unsupported data received. 5 pec_err r/w packet error check failed. 4 crc_err r/w memory fault detect ed (for example, a crc error). 3 proc_err r not supported. 2 reserved r reserved. 1 comm_err r/w other communication fa ult not specified by bits[7:2]. 0 mem_err r/w other memory or logic fault not specified by bits[7:2 ]. this bit is set if the black box record number has been reached (register 0xfe48[2]). status_mfr_specific the status_mfr_specific register returns the status of manufacturer specific faults. a value of 1 in this command indicates tha t a fault has occurred. table 78. register 0x80status_mfr_specific bits bit name r/w description 7 gpio4_fault r/w gpio4 fault received. 6 gpio3_fault r/w gpio3 fault received. 5 gpio2_fault r/w gpio2 fault received. 4 gpio1_fault r/w gpio1 fault received. 3 iin_oc_fast_fault r/w fast input overcurrent fault received. 2 iout_uc_fast_fault r/w fast output reverse current fault received. 1 iout_oc_fast_fault r/w fast output overcurrent current fault received. 0 vout_ov_fast_fault r/w fast output overvoltage fault received. data sheet adp1055 rev. a | page 79 of 140 read_vin the read_vin command returns the input voltage value (v) in linear data format (x = y 2 n ). table 79. register 0x88read_vin bits bit name r/w description [15:11] exponent-n r twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r twos complement y-mantissa used in linear data format (x = y 2 n ). read_iin the read_iin command returns the input current value (a) in linear data format (x = y 2 n ). table 80. register 0x89read_iin bits bit name r/w description [15:11] exponent-n r twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r twos complement y-mantissa used in linear data format (x = y 2 n ). read_vout the read_vout command returns the output voltage value (v) in linear data format (v = y 2 n ). exponent n is set using vout_mode[4:0]. table 81. register 0x8bread_vout bits bit name r/w description [15:0] mantissa-y r unsigned y-mantissa used in output voltage related commands in linear data format (v = y 2 n ). read_iout the read_iout command returns the output current value (a) in linear data format (v = y 2 n ). table 82. register 0x8cread_iout bits bit name r/w description [15:11] exponent-n r twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r twos complement y-mantissa used in linear data format (x = y 2 n ). reserved this register is reserved. table 83. register 0x8dreserved bits bit name r/w description [15:0] reserved r reserved. read_temperature_2 the read_temperature_2 command returns the external 1 (forward diode) temperature (c) in linear data format (x = y 2 n ). table 84. register 0x8eread_temperature_2 bits bit name r/w description [15:11] exponent-n r twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r twos complement y-mantissa used in linear data format (x = y 2 n ). read_temperature_3 the read_temperature_3 command returns the external 2 (reverse diode) temperature (c) in linear data format (x = y 2 n ). table 85. register 0x8fread_temperature_3 bits bit name r/w description [15:11] exponent-n r twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r twos complement y-mantissa used in linear data format (x = y 2 n ). adp1055 data sheet rev. a | page 80 of 140 read_duty_cycle the read_duty_cycle command returns the duty cycle (%) in linear data format (x = y 2 n ). table 86. register 0x94read_duty_cycle bits bit name r/w description [15:11] exponent-n r twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r twos complement y-mantissa used in linear data format (x = y 2 n ). read_frequency the read_frequency command returns the actual switching fr equency value (khz) in linear data format (x = y 2 n ). table 87. register 0x95read_frequency bits bit name r/w description [15:11] exponent-n r twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r twos complement y-mantissa used in linear data format (x = y 2 n ). read_pout the read_pout command returns the output power (w) in linear data format (x = y 2 n ). table 88. register 0x96read_pout bits bit name r/w description [15:11] exponent-n r twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r twos complement y-mantissa used in linear data format (x = y 2 n ). pmbus_revision the pmbus_revision command returns the pmbus version information. the adp1055 is compliant with pmbus revision 1.2. reading this command results in a value of 0x22. table 89. register 0x98pmbus_revision bits bit name r/w description [7:4] part 1 revision r compliant to pmbus part 1 specification: 0010 = revision 1.2. [3:0] part 2 revision r compliant to pmbus part 2 specification: 0010 = revision 1.2. mfr_id the mfr_id register stores the manufacturer id. this register can store 23 bytes. table 90. register 0x99mfr_id bits bit name r/w description [7:0] mfr_id block read/write return the manufacturers id. mfr_model the mfr_model register stores the manufacturer model number. this register can store 19 bytes. table 91. register 0x9amfr_model bits bit name r/w description [7:0] model block read/write return the manufacturers model number. mfr_revision the mfr_revision register stores the manufacturer revision number. this register can store 23 bytes. table 92. register 0x9bmfr_revision bits bit name r/w description [7:0] revision block read/write return the manufacturers revision number. data sheet adp1055 rev. a | page 81 of 140 mfr_location the mfr_location register stores the manufacturer location. this register can store nine bytes. table 93. register 0x9cmfr_location bits bit name r/w description [7:0] location block read/write return the manufacturers location. mfr_date the mfr_date register stores the manufacturer date. this register can store 11 bytes. table 94. register 0x9dmfr_date bits bit name r/w description [7:0] date block read/write return the manufacturers date. mfr_serial the mfr_serial register stores the manufacturer serial number. this register can store 13 bytes. table 95. register 0x9emfr_serial bits bit name r/w description [7:0] serial no block read/write return the manufacturers serial number. ic_device_id the ic_device_id register stores the id and device number of the adp1055 . the default values are 0x02, 0x41, 0x55. table 96. register 0xadic_device_id bits bit name r/w description [7:0] revision block read/write return the ic s id and device number: 0x02, 0x41, 0x55. ic_device_rev the ic_device_rev register stores the device revision number of the adp1055 . the default values are 0x01 and 0xrev. table 97. register 0xaeic_device_rev bits bit name r/w description [7:0] revision block read/write device revision number: 0x01 0x11. eeprom_page_00 through eeprom_page_15 commands register 0xb0 through register 0xbf are read/write block commands. the eeprom_page_00 through eeprom_page_15 commands are used to read data from the eeprom (page 0 through page 15) and to write data to the eeprom (page 6 through page 15). for ex ample, eeprom_page_07 reads from and writes to page 7 of the eeprom main block; eeprom_page_11 reads from and writes to page 11 of the eeprom main block. for more information, see the eeprom section. eeprom_page_00 table 98. register 0xb0eeprom_page_00 bits bit name r/w description [7:0] eeprom_page_00 block read reserved by ma nufacturer for storing the default settings. eeprom_page_01 table 99. register 0xb1eeprom_page_01 bits bit name r/w description [7:0] eeprom_page_01 block read reserved by ma nufacturer for storing the user settings. adp1055 data sheet rev. a | page 82 of 140 eeprom_page_02 table 100. register 0xb2eeprom_page_02 bits bit name r/w description [7:0] eeprom_page_02 block read reserved by manu facturer for storing black box information. eeprom_page_03 table 101. register 0xb3eeprom_page_03 bits bit name r/w description [7:0] eeprom_page_03 block read reserved by manu facturer for storing black box information. eeprom_page_04 table 102. register 0xb4eeprom_page_04 bits bit name r/w description [7:0] eeprom_page_04 block read reserved by manufacturer for storing gui settings. eeprom_page_05 table 103. register 0xb5eeprom_page_05 bits bit name r/w description [7:0] eeprom_page_05 block read reserved by manufa cturer for storing factory tracking settings. eeprom_page_06 table 104. register 0xb6eeprom_page_06 bits bit name r/w description [7:0] eeprom_page_06 block read/write block re ad/write of page 6 of the eeprom main bl ock. the eeprom must first be unlocked. eeprom_page_07 table 105. register 0xb7eeprom_page_07 bits bit name r/w description [7:0] eeprom_page_07 block read/write block re ad/write of page 7 of the eeprom main bl ock. the eeprom must first be unlocked. eeprom_page_08 table 106. register 0xb8eeprom_page_08 bits bit name r/w description [7:0] eeprom_page_08 block read/write block re ad/write of page 8 of the eeprom main bl ock. the eeprom must first be unlocked. eeprom_page_09 table 107. register 0xb9eeprom_page_09 bits bit name r/w description [7:0] eeprom_page_09 block read/write block re ad/write of page 9 of the eeprom main bl ock. the eeprom must first be unlocked. data sheet adp1055 rev. a | page 83 of 140 eeprom_page_10 table 108. register 0xbaeeprom_page_10 bits bit name r/w description [7:0] eeprom_page_10 block read/write block re ad/write of page 10 of the eeprom main bl ock. the eeprom must first be unlocked. eeprom_page_11 table 109. register 0xbbeeprom_page_11 bits bit name r/w description [7:0] eeprom_page_11 block read/write block re ad/write of page 11 of the eeprom main bl ock. the eeprom must first be unlocked. eeprom_page_12 table 110. register 0xbceeprom_page_12 bits bit name r/w description [7:0] eeprom_page_12 block read/write block re ad/write of page 12 of the eeprom main bl ock. the eeprom must first be unlocked. eeprom_page_13 table 111. register 0xbdeeprom_page_13 bits bit name r/w description [7:0] eeprom_page_13 block read/write block re ad/write of page 13 of the eeprom main bl ock. the eeprom must first be unlocked. eeprom_page_14 table 112. register 0xbeeeprom_page_14 bits bit name r/w description [7:0] eeprom_page_14 block read/write block re ad/write of page 14 of the eeprom main bl ock. the eeprom must first be unlocked. eeprom_page_15 table 113. register 0xbfeeprom_page_15 bits bit name r/w description [7:0] eeprom_page_15 block read/write block re ad/write of page 15 of the eeprom main bl ock. the eeprom must first be unlocked. slv_addr_select on first power-up, a read to this command using the general call address (0x00) returns the i 2 c slave address of the adp1055 . any subsequent writes to this register overwrite this information. table 114. register 0xd0slv_addr_select bits bit name r/w description [7:6] reserved r returns 01. [5:4] address, high byte r/w 00 = 0x40 to 0x4f (defaul t address set by selecting resistor on the add pin). 01 = 0x50 to 0x5f. 10 = 0x60 to 0x6f. 11 = 0x70 to 0x7f. [3:0] address, low byte r/w low byte of slave address (determined by the resistor value on the add pin). adp1055 data sheet rev. a | page 84 of 140 eeprom_crc_chksum table 115. register 0xd1eeprom_crc_chksum bits bit name r/w description [7:0] crc checksum r return the crc checksum value from the eeprom download operation. eeprom_num_rd_bytes table 116. register 0xd2eeprom_num_rd_bytes bits bit name r/w description [7:0] number of read bytes returned r/w set the number of read bytes returned when using the eeprom_page_xx commands. eeprom_addr_offset table 117. register 0xd3eeprom_addr_offset bits bit name r/w description [15:0] address offset r/w sets the address offset of the current eeprom page. eeprom_page_erase table 118. register 0xd4eeprom_page_erase bits bit name r/w description [7:0] page erase w perform a page erase on the selected eeprom page (p age 6 to page 15). wait 35 ms after each page erase operation. the eeprom must first be unlock ed. page 0 to page 5 are reserved and their contents must not be erased. eeprom_password table 119. register 0xd5eeprom_password bits bit name r/w description [7:0] eeprom password w write the password to this register two consecutive times to unlock the eeprom and/or to change the eeprom password. the factory default password is 0xff. to lock the eeprom, type any value other than the password to this register. trim_password table 120. register 0xd6trim_password bits bit name r/w description [7:0] trim password w write the password to this register to unlock the trim registers for write access. write the trim password twice to unlock the register; write any other value to exit. the trim password is the same as the eeprom password (0xff). key_code table 121. register 0xd7key_code bits bit name r/w description [31:0] keycode block read/ write write the 32-bit keycode to this command to un lock access to command 0xf4 and command 0xf5. write the key code password twice to unlock the commands; write any other value to lock them. the factory default password is 0xffffffff. the procedur e includes a block write of four bytes. the readback returns five bytes; the fifth byte is 0 if locked or 1 if unlocked. eeprom_info table 122. register 0xf1eeprom_info bits bit name r/w description [7:0] eeprom_info block read block read of the manufacturer data in the eeprom. data sheet adp1055 rev. a | page 85 of 140 read_blackbox_curr table 123. register 0xf2read_blackbox_curr bits bit name r/w description var block read this command returns the data for the current reco rd n (last record saved in the black box). for information about the contents of the black bo x record, see the black box contents section. read_blackbox_prev table 124. register 0xf3read_blackbox_prev bits bit name r/w description var block read this command returns the data for the previous reco rd n ? 1 (next-to-last record saved in the black box). for information about the contents of the black box record, see the black box contents section. cmd_mask the cmd_mask command allows any pmbus command to be masked in the adp1055 . if the command is masked, a read or a write to that command results in a no acknowledge (nack). the store_user_all (register 0x15) and restore_user_all (register 0x16) commands are not maskable. table 125. register 0xf4cmd_mask bits bit name r/w description var command masking block read/write this command can be used to disable (mask) an y of the standard pmbus commands (command 0x01 to command 0xff). to use this command, the correct key code must be written. block count = 0x20 (32 bytes) mask[255:0] = masking status bits. [0] = command 0x00. [255] = command 0xff. extcmd_mask the extcmd_mask command allows any manufacturer specific command to be masked in the adp1055 . if the command is masked, a read or a write to that command results in a no acknowledge (nack). table 126. register 0xf5extcmd_mask bits bit name r/w description var command masking block read/write this command can be used to disable (mask) an y of the manufacturer specific pmbus commands (command 0xfe00 to command 0xfea3). to use this command, the correct key code must be written. block count = 0x15 (21 bytes) mask[167:0] = masking status bits. [0] = command 0xfe00. [167] = command 0xfea7. adp1055 data sheet rev. a | page 86 of 140 manufacturer specific pmbus command descriptions table 127. register 0xfe00go_cmd bits bit name r/w description 7 reserved r/w reserved. 6 sync w this bit latches register 0xfe55. 5 vff w this bit latches register 0xfe29. 4 double update rate, vs balance w this bit latches register 0xfe57 and register 0xfe25. 3 filter go w this bit latches register 0xfe4a, register 0x fe01 to register 0xfe0c, register 0xfe5e, and register 0xfe66. 2 frequency go w update switching frequency programmed by frequency_switch command (register 0x33). 1 pwm go w update register 0xfe0d to register 0xfe1c, register 0xfe1f to register 0xfe24, and register 0xfe15 to register 0xfe1c 0 voltage reference go w update reference voltage commanded by the vout_command (register 0x21). figure 85. digital filter programmability table 128. register 0xfe01nm_digfilt_lf_gain_setting (requires use of the go bit in register 0xfe00) bits bit name r/w description [7:0] lf gain setting r/w this register determines the low frequency gain of the loop response in normal mode. it is programmable over a 20 db range. each lsb corresponds to a 0.3 db increase. see figure 85. table 129. register 0xfe02nm_digfilt_zero_setting (r equires use of the go bit in register 0xfe00) bits bit name r/w description [7:0] zero setting r/w this register determines the posit ion of the final zero in normal mode. see figure 85. table 130. register 0xfe03nm_digfilt_pole_setting (r equires use of the go bit in register 0xfe00) bits bit name r/w description [7:0] pole setting r/w this register determines the pos ition of the final pole in normal mode. see figure 85. table 131. register 0xfe04nm_digfilt_hf_gain_setting (requires use of the go bit in register 0xfe00) bits bit name r/w description [7:0] hf gain setting r/w this register determines the high frequency gain of the loop response in normal mode. it is programmable over a 20 db range. each lsb corresponds to a 0.3 db increase. see figure 85. table 132. register 0xfe05llm_digfilt_lf_gain_setting (requires use of the go bit in register 0xfe00) bits bit name r/w description [7:0] lf gain setting r/w this register determines the low frequency gain of the loop response in light load mode. it is programmable over a 20 db range. each lsb corresponds to a 0.3 db increase. see figure 85. pole location range zero zero range 20db pole lf gain range 20db 20db hf gain range 100hz 500hz 1khz 5khz 10khz 12004-085 data sheet adp1055 rev. a | page 87 of 140 table 133. register 0xfe06llm_digfilt_zero_setting (r equires use of the go bit in register 0xfe00) bits bit name r/w description [7:0] zero setting r/w this register determines the positio n of the final zero in light load mode. see figure 85. table 134. register 0xfe07llm_digfilt_pole_setting (r equires use of the go bit in register 0xfe00) bits bit name r/w description [7:0] pole setting r/w this register determines the posit ion of the final pole in light load mode. see figure 85. table 135. register 0xfe08llm_digfilt_hf_gain_setting (requires use of the go bit in register 0xfe00) bits bit name r/w description [7:0] hf gain setting r/w this register determines the high frequency gain of the loop response in light load mode. it is programmable over a 20 db range. each lsb corresponds to a 0.3 db increase. see figure 85. table 136. register 0xfe09ss_digfilt_lf_gain_setting (requires use of the go bit in register 0xfe00) bits bit name r/w description [7:0] lf gain setting r/w this register determines the low frequency gain of the loop response in soft start mode. it is programmable over a 20 db range. each lsb corresponds to a 0.3 db increase. see figure 85. table 137. register 0xfe0ass_digfilt_zero_setting (r equires use of the go bit in register 0xfe00) bits bit name r/w description [7:0] zero setting r/w this register determines the positio n of the final zero in soft start mode. see figure 85. table 138. register 0xfe0bss_digfilt_pole_setting (requires use of the go bit in register 0xfe00) bits bit name r/w description [7:0] pole setting r/w this register determines the position of the final pole in soft start mode. see figure 85. table 139. register 0xfe0css_digfilt_hf_gain_setting (requires use of the go bit in register 0xfe00) bits bit name r/w description [7:0] hf gain setting r/w this register determines the high frequency gain of the loop response in soft start mode. it is programmable over a 20 db range. each lsb corresponds to a 0.3 db increase. see figure 85. table 140. register 0xfe0d, register 0xfe0f, regi ster 0xfe11, register 0xfe13outa_redge_setting, outb_redge_setting, outc_redge_setting , outd_redge_setting (requires use of the go bit in register 0xfe00) bits bit name r/w description [15:4] t 1 , t 3 , t 5 , t 7 r/w this register contains the 12-bit t 1 , t 3 , t 5 , t 7 time. each lsb corresponds to 5 ns resolution. the minimum and maximum possible duty cycle is 0% and 100%, respectively. 3 modulate enable r/w 1 = pwm modulation acts on the t 1 , t 3 , t 5 , t 7 edge. 0 = no pwm modulation of the t 1 , t 3 , t 5 , t 7 edge. 2 t 1 , t 3 , t 5 , t 7 sign r/w 1 = negative sign. increase of pwm modulation moves t 1 , t 3 , t 5 , t 7 right. 0 = positive sign. increase of pwm modulation moves t 1 , t 3 , t 5 , t 7 left. [1:0] reserved r reserved. table 141. register 0xfe0e, register 0xfe10, regi ster 0xfe12, register 0xfe14outa_fedge_setting, outb_fedge_setting, outc_fedge_setting, outd_fedge_setti ng (requires use of the go bit in register 0xfe00) bits bit name r/w description [15:4] t 2 , t 4 , t 6 , t 8 r/w this register contains the 12-bit t 2 , t 4 , t 6 , t 8 time. each lsb corresponds to 5 ns resolution. the minimum and maximum possible duty cycle is 0% and 100%, respectively. 3 modulate enable r/w 1 = pwm modulation acts on the t 2 , t 4 , t 6 , t 8 edge. 0 = no pwm modulation of the t 2 , t 4 , t 6 , t 8 edge. 2 t 2 , t 4 , t 6 , t 8 sign r/w 1 = negative sign. increase of pwm modulation moves t 2 , t 4 , t 6 , t 8 right. 0 = positive sign. increase of pwm modulation moves t 2 , t 4 , t 6 , t 8 left. [1:0] reserved r reserved. adp1055 data sheet rev. a | page 88 of 140 table 142. register 0xfe15, register 0xfe17sr1_redge_setti ng, sr2_redge_setting (requires use of the go bit in register 0xfe00) bits bit name r/w description [15:4] t 9 , t 11 r/w this register contains the 12-bit t 9 , t 11 time. each lsb corresponds to 5 ns resolution. the minimum and maximum possible duty cycle is 0% and 100%, respectively. 3 modulate enable r/w 1 = pwm modulation acts on the t 9 , t 11 edge. 0 = no pwm modulation of the t 9 , t 11 edge. 2 t 9 , t 11 sign r/w 1 = negative sign. increase of pwm modulation moves t 9 , t 11 right. 0 = positive sign. increase of pwm modulation moves t 9 , t 11 left. [1:0] reserved r reserved. table 143. register 0xfe16, register 0xfe18sr1_fedge_setti ng, sr2_fedge_setting (requires use of the go bit in register 0xfe00) bits bit name r/w description [15:4] t 10 , t 12 r/w this register contains the 12-bit t 10 , t 12 time. each lsb corresponds to 5 ns resolution. 3 modulate enable r/w 1 = pwm modulation acts on the t 10 , t 12 edge. 0 = no pwm modulation of the t 10 , t 12 edge. 2 t 10 , t 12 sign r/w 1 = negative sign. increase of pwm modulation moves t 10 , t 12 right. 0 = positive sign. increase of pwm modulation moves t 10 , t 12 left. [1:0] reserved r reserved. table 144. register 0xfe19, register 0xfe1bsr1_redge_ llm_setting, sr2_redge_llm_setting (requires use of the go bit in register 0xfe00) bits bit name r/w description [15:4] t 9 , t 11 r/w this register contains the 12-bit t 9 , t 11 time. each lsb corresponds to 5 ns resolution. this is the sr setting in light load mode. the minimum and maximum possible duty cycle is 0% and 100%, respectively. 3 modulate enable r/w 1 = pwm modulation acts on the t 9 , t 11 edge. 0 = no pwm modulation of the t 9 , t 11 edge. 2 t 9 , t 11 sign r/w 1 = negative sign. increase of pwm modulation moves t 9 , t 11 right. 0 = positive sign. increase of pwm modulation moves t 9 , t 11 left. [1:0] reserved r reserved. table 145. register 0xfe1a, register 0xfe1csr1_fedge_ llm_setting, sr2_fedge_llm_setting (requires use of the go bit in register 0xfe00) bits bit name r/w description [15:4] t 10 , t 12 r/w this register contains the 12-bit t 10 , t 12 time. each lsb corresponds to 5 ns resolution. this is the sr setting in light load mode. the minimum and maximum possible duty cycle is 0% and 100%, respectively. 3 modulate enable r/w 1 = pwm modulation acts on the t 10 , t 12 edge. 0 = no pwm modulation of the t 10 , t 12 edge. 2 t 10 , t 12 sign r/w 1 = negative sign. increase of pwm modulation moves t 10 , t 12 right. 0 = positive sign. increase of pwm modulation moves t 10 , t 12 left. [1:0] reserved r reserved. data sheet adp1055 rev. a | page 89 of 140 table 146. register 0xfe1dadt_config bits bit name r/w description 7 averaging period r/w 1 = 9-bit averaging (327 s). 0 = 12-bit averaging (2.6 ms). 6 adt reference r/w 0 = cs1 as reference. 1 = cs2 as reference. [5:3] update rate r/w the adt algorithm adjusts the dead time in step s of 5 ns. these bits are used to program the number of pwm switching cycles between each step. the number is calculated as 2 n + 1, where n is the 3-bit value specified by these bits. if n = 6 (110), each pwm edge is adjusted by 5 ns every 2 6 + 1 = 65 switching cycles. [2:0] multiplier r/w these bits specify the programming step for regist er 0xfe1f to register 0xfe22, bits[6:4] and bits[2:0]. bit 2 bit 1 bit 0 multiplier 0 0 0 5 0 0 1 10 0 1 0 15 0 1 1 20 1 0 0 25 1 0 1 30 1 1 0 35 1 1 1 40 table 147. register 0xfe1eadt_threshold bits bit name r/w description [7:0] adaptive dead time threshold r/w this register sets the adt threshold. this 8-bi t number is compared to the eight msbs of the cs1/cs2 value register. when the current level measured on cs1/cs2 falls below this threshold, the edges of the pwm signals are affected as a linear function of the cs1/cs2 current, as programmed in register 0xfe1f to register 0xfe24. when this register is pr ogrammed to 0x00, the adt function is disabled. when cs1 is used as the reference, each lsb in this register corresponds to 1.6 v/2 8 = 6.25 mv. when cs2 is used as the reference, each lsb in this register corresponds to 26.25 mv, 52.5 mv, or 420 mv]/2 8 = 102.539 v, 205.078 v, or 1640.625 v. also note that when cs2 is used as the reference, the maximum allowed value in this register is 224 (0xe0). table 148. register 0xfe1f, register 0xfe20, register 0xfe21, register 0xfe22outa _dead_time, outb_dead_time, outc_dead_time, outd_dead_time (requires use of the go bit in register 0xfe00) bits bit name r/w description 7 t 1 , t 3 , t 5 , t 7 , t 9 , t 11 polarity r/w 0 = positive polarity. 1 = negative polarity. [6:4] t 1 , t 3 , t 5 , t 7 , t 9 , t 11 offset r/w this value multiplied by register 0x fe1d[2:0] determines the offset for t 1 , t 3 , t 5 , t 7 , t 9 , t 11 from nominal timing at no load. bit 6 bit 5 bit 4 offset (ns) 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 3 t 2 , t 4 , t 6 , t 8 , t 10 , t 12 polarity r/w 0 = positive polarity. 1 = negative polarity. adp1055 data sheet rev. a | page 90 of 140 bits bit name r/w description [2:0] t 2 , t 4 , t 6 , t 8 , t 10 , t 12 offset r/w this value multiplied by register 0x fe1d[2:0] determines the offset for t 2 , t 4 , t 6 , t 8 , t 10 , t 12 from nominal timing at no load. bit 2 bit 1 bit 0 offset (ns) 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 table 149. register 0xfe23, register 0xfe24sr1_dead_time, sr2_d ead_time (requires use of the go bit in register 0xfe00) bits bit name r/w description 7 t 9 , t 11 polarity r/w 0 = positive polarity. 1 = negative polarity. [6:4] t 9 , t 11 offset r/w this value multiplied by register 0x fe1d[2:0] determines the offset for t 1 , t 3 , t 5 , t 7 , t 9 , t 11 from nominal timing at no load. bit 6 bit 5 bit 4 offset (ns) 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 3 t 10 , t 12 polarity r/w 0 = positive polarity. 1 = negative polarity. [2:0] t 10 , t 12 offset r/w this value multiplied by register 0x fe1d[2:0] determines the offset for t 2 , t 4 , t 6 , t 8 , t 10 , t 12 from nominal timing at no load. bit 2 bit 1 bit 0 offset (ns) 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 table 150. register 0xfe25vsbal_setting (requi res use of the go bit in register 0xfe00) bits bit name r/w description 7 reserved r reserved. 6 volt-second balance enable r/w setting this bit enables volt-second balance for the main transformer (used for full-bridge configurations). 5 reserved r set to 0 for proper operation. 4 volt-second disable during soft start r/w 0 = do not blank volt-second balance control during soft start (recommended). 1 = blank volt-second balance control during soft start. 3 reserved r reserved. 2 reserved r reserved. data sheet adp1055 rev. a | page 91 of 140 bits bit name r/w description [1:0] volt-second balance gain setting r/w these bits set the gain of the volt-second balance circuit. the gain can be changed by a factor of 64. when these bits are set to 00, it takes approximately 700 ms to achieve volt-second balance. when these bits are set to 11, it takes approximately 10 ms to achieve volt-second balance. bit 1 bit 0 volt-second balance gain 0 0 1 0 1 4 1 0 16 1 1 64 table 151. register 0xfe26vsbal_outa_b bits bit name r/w description 7 modulate enable, t 1 r/w setting this bit enables modulation from balance control on the outa rising edge, t 1 . 6 t 1 sign r/w 0 = positive sign. increase of balance control modulation moves t 1 right. 1 = negative sign. increase of balance control modulation moves t 1 left. 5 modulate enable, t 2 r/w setting this bit enables modulation from balance control on the outa falling edge, t 2 . 4 t 2 sign r/w 0 = positive sign. increase of balance control modulation moves t 2 right. 1 = negative sign. increase of balance control modulation moves t 2 left. 3 modulate enable, t 3 r/w setting this bit enables modulation from balance control on the outb rising edge, t 3 . 2 t 3 sign r/w 0 = positive sign. increase of balance control modulation moves t 3 right. 1 = negative sign. increase of balance control modulation moves t 3 left. 1 modulate enable, t 4 r/w setting this bit enables modulation from balance control on the outb falling edge, t 4 . 0 t 4 sign r/w 0 = positive sign. increase of balance control modulation moves t 4 right. 1 = negative sign. increase of balance control modulation moves t 4 left. table 152. register 0xfe27vsbal_outc_d bits bit name r/w description 7 modulate enable, t 5 r/w setting this bit enables modulation from balance control on the outc rising edge, t 5 . 6 t 5 sign r/w 0 = positive sign. increase of balance control modulation moves t 5 right. 1 = negative sign. increase of balance control modulation moves t 5 left. 5 modulate enable, t 6 r/w setting this bit enables modulation from balance control on the outc falling edge, t 6 . 4 t 6 sign r/w 0 = positive sign. increase of balance control modulation moves t 6 right. 1 = negative sign. increase of balance control modulation moves t 6 left. 3 modulate enable, t 7 r/w setting this bit enables modulation from balance control on the outd rising edge, t 7 . 2 t 7 sign r/w 0 = positive sign. increase of balance control modulation moves t 7 right. 1 = negative sign. increase of balance control modulation moves t 7 left. 1 modulate enable, t 8 r/w setting this bit enables modulation from balance control on the outd falling edge, t 8 . 0 t 8 sign r/w 0 = positive sign. increase of balance control modulation moves t 8 right. 1 = negative sign. increase of balance control modulation moves t 8 left. table 153. register 0xfe28vsbal_sr1_2 bits bit name r/w description 7 modulate enable, t 9 r/w setting this bit enables modulation from balance control on the sr1 rising edge, t 9 . 6 t 9 sign r/w 0 = positive sign. increase of balance control modulation moves t 9 right. 1 = negative sign. increase of balance control modulation moves t 9 left. 5 modulate enable, t 10 r/w setting this bit enables modulation from balance control on the sr1 falling edge, t 10 . 4 t 10 sign r/w 0 = positive sign. increase of balance control modulation moves t 10 right. 1 = negative sign. increase of balance control modulation moves t 10 left. 3 modulate enable, t 11 r/w setting this bit enables modulation from balance control on the sr2 rising edge, t 11 . 2 t 11 sign r/w 0 = positive sign. increase of balance control modulation moves t 11 right. 1 = negative sign. increase of balance control modulation moves t 11 left. 1 modulate enable, t 12 r/w setting this bit enables modulation from balance control on the sr2 falling edge, t 12 . 0 t 12 sign r/w 0 = positive sign. increase of balance control modulation moves t 12 right. 1 = negative sign. increase of balance control modulation moves t 12 left. adp1055 data sheet rev. a | page 92 of 140 table 154. register 0xfe29ffwd_setting (require s use of the go bit in register 0xfe00) bits bit name r/w description [7:4] reserved r/w reserved. 3 disable feedforward during soft start r/w if voltage line feedforward is enabled, this bit disables it during the soft start process. this operation is gated by the filter go bit (register 0xfe00). 0 = feedforward enabled during soft start (recommended setting). 1 = feedforward disabled during soft start. 2 feedforward enable r/w this bit enables the voltage line feedforward loop. this operation is gated by the filter go bit (register 0xfe00]). 0 = feedforward disabled. 1 = feedforward enabled. 1 lf 8 gain increase r/w 0 = default. 1 = 8 lf gain. 0 global bit for nonlinear gain r/w 0 = 1/1.25/1.5/2 gain. 1 = 1/2/3/4 gain. table 155. register 0xfe2aishare_setting bits bit name r/w description [7:4] number of bits dropped by master r/w these bits determine how much a master device reduces its output voltage to maintain current sharing. each lsb corresponds to 1.6 v/2 16 = 24 v (at the vs pins). this lsb is multiplied or divided by the setting in the share bus bandwidth register. [3:0] bit difference between master and slave r/w these bits determine how closely a slave tries to match the current of the master device. the higher the setting, the larger the voltage difference that satisfies the current sharing criteria. table 156. register 0xfe2bishare_bandwidth bits bit name r/w description [7:5] reserved r reserved. 4 bitstream r/w 1 = the current sense adc reading is output on th e ishare pin. this bit stream can be used for analog current sharing. (recommended setting for standalone power supplies). 0 = the digital share bus signal is output on the ishare pin. this signal can be used for digital current sharing. 3 current share select r/w 1 = cs1 reading used for current share. 0 = cs2 reading used for current share. [2:0] share bus bandwidth r/w these bits determine the amount of bandwidth dedicated to the share bus. the value 000 is the lowest possible bandwidth, and the valu e 111 is the highest possible bandwidth. the slave moves up 1 lsb for every share bus transaction (that is, eight data bits plus the start and stop bits). the master moves down x lsbs per share bus transaction, where x is the share bus register setting (register 0xfe2a[7:4]). 0 = divide lsb by 16 (1 lsb = 24 v/16). 1 = divide lsb by 8. 2 = divide lsb by 4. 3 = divide lsb by 2. 4 = nominal. 5 = multiply lsb by 2. 6 = multiply lsb by 4. 7 = multiply lsb by 8. 8 = multiply lsb by 16. data sheet adp1055 rev. a | page 93 of 140 table 157. register 0xfe2ciin_oc_fast_setting bits bit name r/w description [7:3] reserved r reserved. 2 threshold r/w 0 = 1.2 v range. 1 = 250 mv range. [1:0] debounce r/w bit 1 bit 0 debounce time 0 0 0 ns 0 1 40 ns 1 0 80 ns 1 1 120 ns table 158. register 0xfe2diout_oc_fast_setting bits bit name r/w description [7:2] threshold r/w when the adc range is 480 mv, lsb = 600/63 = 9.52 mv. when the adc range is 30 mv or 60 mv, lsb = 60/63 = 0.952 mv. threshold = lsb register 0xfe2d[7:2]. [1:0] debounce r/w bit 1 bit 0 debounce time 0 0 0 ns 0 1 40 ns 1 0 200 ns 1 1 400 ns table 159. register 0xfe2eiout_uc_fast_setting bits bit name r/w description [7:2] threshold r/w |lsb| = 30/63 = 0.476 mv. range is +30 mv to ?30 mv in 64 steps. polarity = 0: threshold = ? 0.477 mv register 0xfe2e[7:2]. polarity = 1: threshold = + 0.472 mv register 0xfe2e [7:2]. note that the iout_uc_fast fault is set when the cs2 reverse comparator is asserted for the minimum debounce programmed time. once set, the iout_uc_fast fault is cleared from 327 s to 656 s following the deassertion of the cs2 reverse comparator. 1 polarity r/w 1 = 0 to +30 mv range. 0 = 0 to ?30 mv range. 0 debounce r/w the debounce setting is set by register 0xfe2d[1:0 ]. for example, if register 0xfe2d[1:0] = 10, the iout_oc_fast_setting is 200 ns and the iout_uc_fast_setting is 800 ns. 00 = 40 ns. 01 = 200 ns. 10 = 800 ns. 11 = 1200 ns. table 160. register 0xfe2fvout_ov_fast_setting bits bit name r/w description [7:2] threshold r/w 64 steps: threshold = 0.8 + (register 0xfe2f[7:2]) 0.8/63. [1:0] debounce r/w these bits set the debounce time. bit 1 bit 0 typical debounce time 0 0 40 ns 0 1 2 s + 1 s 1 0 5 s + 1 s 1 1 10 s + 1 s adp1055 data sheet rev. a | page 94 of 140 table 161. register 0xfe30debounce_setting_1 bits bit name r/w description [15:14] iout_oc_lv_deb r/w these bits set th e debounce time for the iout_oc_lv fault. bit 15 bit 14 debounce 0 0 0 0 1 1 ms + 10 s 1 0 10 ms + 100 s 1 1 100 ms + 1 ms [13:11] vin_uv_deb r/w these bits set th e debounce time for the vin_uv fault. bit 13 bit 12 bit 11 debounce 0 0 0 0 0 0 1 1 ms + 10 s 0 1 0 2.5 ms + 10 s 0 1 1 5 ms + 10 s 1 0 0 10 ms + 100 s 1 0 1 50 ms + 100 s 1 1 0 100 ms + 1 ms 1 1 1 250 ms + 1 ms [10:8] vout_uv_deb r/w these bits set th e debounce time for the vout_uv fault. bit 10 bit 9 bit 8 debounce 0 0 0 0 0 0 1 1 ms + 10 s 0 1 0 2.5 ms + 10 s 0 1 1 5 ms + 10 s 1 0 0 10 ms + 100 s 1 0 1 50 ms + 100 s 1 1 0 100 ms + 1 ms 1 1 1 250 ms + 1 ms [7:4] vin_ov_deb r/w these bits set the debounce time for the vin_ov fault. bit 7 bit 6 bit 5 bit 4 debounce 0 0 0 0 0 0 0 0 1 100 s + 1 s 0 0 1 0 250 s + 1 s 0 0 1 1 500 s + 1 s 0 1 0 0 750 s + 10 s 0 1 0 1 1 ms + 10 s 0 1 1 0 2.5 ms + 10 s 0 1 1 1 5 ms + 10 s 1 0 0 0 7.5 ms + 100 s 1 0 0 1 10 ms + 100 s 1 0 1 0 25 ms + 100 s 1 0 1 1 50 ms + 100 s 1 1 0 0 75 ms + 1 ms 1 1 0 1 100 ms + 1 ms 1 1 1 0 250 ms + 1 ms 1 1 1 1 500 ms + 1 ms data sheet adp1055 rev. a | page 95 of 140 bits bit name r/w description [3:0] vout_ov_deb r/w these bits set the debounce time for the vout_ov fault. bit 3 bit 2 bit 1 bit 0 debounce 0 0 0 0 0 0 0 0 1 100 s + 1 s 0 0 1 0 250 s + 1 s 0 0 1 1 500 s + 1 s 0 1 0 0 750 s + 10 s 0 1 0 1 1 ms + 10 s 0 1 1 0 2.5 ms + 10 s 0 1 1 1 5 ms + 10 s 1 0 0 0 7.5 ms + 100 s 1 0 0 1 10 ms + 100 s 1 0 1 0 25 ms + 100 s 1 0 1 1 50 ms + 100 s 1 1 0 0 75 ms + 1 ms 1 1 0 1 100 ms + 1 ms 1 1 1 0 250 ms + 1 ms 1 1 1 1 500 ms + 1 ms table 162. register 0xfe31debounce_setting_2 bits bit name r/w description [15:12] ishare_deb r/w these bits set th e debounce time for the ishare fault. bit 15 bit 14 bit 13 bit 12 debounce 0 0 0 0 0 0 0 0 1 1 ms + 10 s 0 0 1 0 2.5 ms + 10 s 0 0 1 1 5 ms + 10 s 0 1 0 0 7.5 ms + 100 s 0 1 0 1 10 ms + 100 s 0 1 1 0 25 ms + 100 s 0 1 1 1 50 ms + 100 s 1 0 0 0 75 ms + 1 ms 1 0 0 1 100 ms + 1 ms 1 0 1 0 250 ms + 1 ms 1 0 1 1 500 ms + 1 ms 1 1 0 0 750 ms + 10 ms 1 1 0 1 1 sec + 10 ms 1 1 1 0 2.5 sec + 10 ms 1 1 1 1 5 sec + 10 ms adp1055 data sheet rev. a | page 96 of 140 bits bit name r/w description [11:8] iin_oc_deb r/w these bits set th e debounce time for the iin_oc fault. bit 11 bit 10 bit 9 bit 8 debounce 0 0 0 0 0 0 0 0 1 1 ms + 10 s 0 0 1 0 2.5 ms + 10 s 0 0 1 1 5 ms + 10 s 0 1 0 0 7.5 ms + 100 s 0 1 0 1 10 ms + 100 s 0 1 1 0 25 ms + 100 s 0 1 1 1 50 ms + 100 s 1 0 0 0 75 ms + 1 ms 1 0 0 1 100 ms + 1 ms 1 0 1 0 250 ms + 1 ms 1 0 1 1 500 ms + 1 ms 1 1 0 0 750 ms + 10 ms 1 1 0 1 1 sec + 10 ms 1 1 1 0 2.5 sec + 10 ms 1 1 1 1 5 sec + 10 ms [7:4] iout_uc_deb r/w these bits set th e debounce time for the iout_uc fault. bit 7 bit 6 bit 5 bit 4 debounce 0 0 0 0 0 0 0 0 1 1 ms + 10 s 0 0 1 0 2.5 ms + 10 s 0 0 1 1 5 ms + 10 s 0 1 0 0 7.5 ms + 100 s 0 1 0 1 10 ms + 100 s 0 1 1 0 25 ms + 100 s 0 1 1 1 50 ms + 100 s 1 0 0 0 75 ms + 1 ms 1 0 0 1 100 ms + 1 ms 1 0 1 0 250 ms + 1 ms 1 0 1 1 500 ms + 1 ms 1 1 0 0 750 ms + 10 ms 1 1 0 1 1 sec + 10 ms 1 1 1 0 2.5 sec + 10 ms 1 1 1 1 5 sec + 10 ms data sheet adp1055 rev. a | page 97 of 140 bits bit name r/w description [3:0] iout_oc_deb r/w these bits set th e debounce time for the iout_oc fault. bit 3 bit 2 bit 1 bit 0 debounce 0 0 0 0 0 0 0 0 1 1 ms + 10 s 0 0 1 0 2.5 ms + 10 s 0 0 1 1 5 ms + 10 s 0 1 0 0 7.5 ms + 100 s 0 1 0 1 10 ms + 100 s 0 1 1 0 25 ms + 100 s 0 1 1 1 50 ms + 100 s 1 0 0 0 75 ms + 1 ms 1 0 0 1 100 ms + 1 ms 1 0 1 0 250 ms + 1 ms 1 0 1 1 500 ms + 1 ms 1 1 0 0 750 ms + 10 ms 1 1 0 1 1 sec + 10 ms 1 1 1 0 2.5 sec + 10 ms 1 1 1 1 5 sec + 10 ms table 163. register 0xfe32debounce_setting_3 bits bit name r/w description [15:12] reserved r reserved. [11:8] pout_op_deb r/w these bits set th e debounce time for the pout_op fault. bit 11 bit 10 bit 9 bit 8 debounce 0 0 0 0 0 0 0 0 1 100 s + 1 s 0 0 1 0 250 s + 1 s 0 0 1 1 500 s + 1 s 0 1 0 0 750 s + 10 s 0 1 0 1 1 ms + 10 s 0 1 1 0 2.5 ms + 10 s 0 1 1 1 5 ms + 10 s 1 0 0 0 7.5 ms + 100 s 1 0 0 1 10 ms + 100 s 1 0 1 0 25 ms + 100 s 1 0 1 1 50 ms + 100 s 1 1 0 0 75 ms + 1 ms 1 1 0 1 100 ms + 1 ms 1 1 1 0 250 ms + 1 ms 1 1 1 1 500 ms + 1 ms adp1055 data sheet rev. a | page 98 of 140 bits bit name r/w description [7:4] ton_max_deb r/w these bits set the debounce time for the ton_max fault. bit 7 bit 6 bit 5 bit 4 debounce 0 0 0 0 0 0 0 0 1 100 s + 1 s 0 0 1 0 250 s + 1 s 0 0 1 1 500 s + 1 s 0 1 0 0 750 s + 10 s 0 1 0 1 1 ms + 10 s 0 1 1 0 2.5 ms + 10 s 0 1 1 1 5 ms + 10 s 1 0 0 0 7.5 ms + 100 s 1 0 0 1 10 ms + 100 s 1 0 1 0 25 ms + 100 s 1 0 1 1 50 ms + 100 s 1 1 0 0 75 ms + 1 ms 1 1 0 1 100 ms + 1 ms 1 1 1 0 250 ms + 1 ms 1 1 1 1 500 ms + 1 ms [3:0] ot_deb r/w these bits set the debou nce time for the overtemperature fault. bit 3 bit 2 bit 1 bit 0 debounce 0 0 0 0 0 0 0 0 1 1 ms + 10 s 0 0 1 0 2.5 ms + 10 s 0 0 1 1 5 ms + 10 s 0 1 0 0 7.5 ms + 100 s 0 1 0 1 10 ms + 100 s 0 1 1 0 25 ms + 100 s 0 1 1 1 50 ms + 100 s 1 0 0 0 75 ms + 1 ms 1 0 0 1 100 ms + 1 ms 1 0 1 0 250 ms + 1 ms 1 0 1 1 500 ms + 1 ms 1 1 0 0 750 ms + 10 ms 1 1 0 1 1 sec + 10 ms 1 1 1 0 2.5 sec + 10 ms 1 1 1 1 5 sec + 10 ms data sheet adp1055 rev. a | page 99 of 140 table 164. register 0xfe33debounce_setting_4 bits bit name r/w description [15:12] gpio4_deb r/w these bits set the debounce time for the gpio4 fault. bit 15 bit 14 bit 13 bit 12 debounce 0 0 0 0 0 0 0 0 1 80 ns 0 0 1 0 1 s + 1 s 0 0 1 1 100 s + 1 s 0 1 0 0 500 s + 1 s 0 1 0 1 1 ms + 10 s 0 1 1 0 2.5 ms + 10 s 0 1 1 1 5 ms + 10 s 1 0 0 0 7.5 ms + 100 s 1 0 0 1 10 ms + 100 s 1 0 1 0 25 ms + 100 s 1 0 1 1 50 ms + 100 s 1 1 0 0 75 ms + 1 ms 1 1 0 1 100 ms + 1 ms 1 1 1 0 250 ms + 1 ms 1 1 1 1 500 ms + 1 ms [11:8] gpio3_deb r/w these bits set the debounce time for the gpio3 fault. bit 11 bit 10 bit 9 bit 8 debounce 0 0 0 0 0 0 0 0 1 80 ns 0 0 1 0 1 s + 1 s 0 0 1 1 100 s + 1 s 0 1 0 0 500 s + 1 s 0 1 0 1 1 ms + 10 s 0 1 1 0 2.5 ms + 10 s 0 1 1 1 5 ms + 10 s 1 0 0 0 7.5 ms + 100 s 1 0 0 1 10 ms + 100 s 1 0 1 0 25 ms + 100 s 1 0 1 1 50 ms + 100 s 1 1 0 0 75 ms + 1 ms 1 1 0 1 100 ms + 1 ms 1 1 1 0 250 ms + 1 ms 1 1 1 1 500 ms + 1 ms adp1055 data sheet rev. a | page 100 of 140 bits bit name r/w description [7:4] gpio2_deb r/w these bits set the debounce time for the gpio2 fault. bit 7 bit 6 bit 5 bit 4 debounce 0 0 0 0 0 0 0 0 1 80 ns 0 0 1 0 1 s + 1 s 0 0 1 1 100 s + 1 s 0 1 0 0 500 s + 1 s 0 1 0 1 1 ms + 10 s 0 1 1 0 2.5 ms + 10 s 0 1 1 1 5 ms + 10 s 1 0 0 0 7.5 ms + 100 s 1 0 0 1 10 ms + 100 s 1 0 1 0 25 ms + 100 s 1 0 1 1 50 ms + 100 s 1 1 0 0 75 ms + 1 ms 1 1 0 1 100 ms + 1 ms 1 1 1 0 250 ms + 1 ms 1 1 1 1 500 ms + 1 ms [3:0] gpio1_deb r/w these bits set the debounce time for the gpio1 fault. bit 3 bit 2 bit 1 bit 0 debounce 0 0 0 0 0 0 0 0 1 80 ns 0 0 1 0 1 s + 1 s 0 0 1 1 100 s + 1 s 0 1 0 0 500 s + 1 s 0 1 0 1 1 ms + 10 s 0 1 1 0 2.5 ms + 10 s 0 1 1 1 5 ms + 10 s 1 0 0 0 7.5 ms + 100 s 1 0 0 1 10 ms + 100 s 1 0 1 0 25 ms + 100 s 1 0 1 1 50 ms + 100 s 1 1 0 0 75 ms + 1 ms 1 1 0 1 100 ms + 1 ms 1 1 1 0 250 ms + 1 ms 1 1 1 1 500 ms + 1 ms data sheet adp1055 rev. a | page 101 of 140 the vout_ov_fast_fault_response command instructs the device on the actions to take due to an output fast overvoltage fault condition. the device notifies the host and sets the none_of_the_above bit in status_byte register, the mfr_specific bit in status_word register, and the vout_ov_fast_fault bit in status_mfr_specific register. table 165. register 0xfe34vout_ov_fast_fault_response bits bit name r/w description [7:6] response r/w determines the device res ponse to a fast overvo ltage fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the delay time (bits[2:0]). if the fault persists, retry the number of times specified by bits[5:3]. 1 0 shut down, disable the output, and re spond as programmed in the retry setting (bits[5:3]). 1 1 disable the output while th e fault is present. operation resumes and the output is enabled when the faul t condition no longer exists. [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay time r/w number of delay time units (see register 0xfe3e). the iout_oc_fast_fault_response command instructs the device on the actions to take due to an output fast overcurrent fault condition. the device notifies the host and sets the none_of_the_above bit in status_byte register, the mfr_specific bit in status_word register, and the iout_oc_fast_fault bit in status_mfr_specific register. table 166. register 0xfe35iout_oc_fast_fault_response bits bit name r/w description [7:6] response r/w determines the device res ponse to a fast overcurrent fault condition. bit 7 bit 6 response 0 0 operate in current limiting mode, maintaining the output current at iout_oc_fault_limit. 0 1 operate in current limiting mode, maintaining the output current at iout_oc_fault_limit. if v out falls below the iout_oc_lv_fault_limit, respond as programmed by the retry setting (bits[5:3]). 1 0 continue operation in current limiting mode for the delay time (bits[2:0]). if the device is still in current limiting mode, respond as pr ogrammed by the retry setting (bits[5:3]). 1 1 shut down, disable the output, and respond as programmed by the retry setting (bits[5:3]). [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w number of delay time units (see register 0xfe3e). adp1055 data sheet rev. a | page 102 of 140 the iout_uc_fast_fault_response command instructs the device on the actions to take due to an output fast undercurrent fault condition. the device notifies the host and sets the none_of_the_above bit in status_byte register, the mfr_specific bit in status_word register, and the iout_uc_fast_fault bit in status_mfr_specific register. table 167. register 0xfe36iout_uc_fast_fault_response bits bit name r/w description [7:6] response r/w determines the device respon se to a fast undercurrent fault condition. bit 7 bit 6 response 0 0 operate in current limiting mode, maintaining the output current at iout_oc_fault_limit. 0 1 operate in current limiting mode, maintaining the output current at iout_oc_fault_limit. if v out falls below the iout_oc_lv_fault_limit, respond as programmed by the retry setting (bits[5:3]). 1 0 continue operation in current limiting mode for the delay time (bits[2:0]). if the device is still in current limiting mode , respond as programmed by the retry setting (bits[5:3]). 1 1 shut down, disable the output, and re spond as programmed by the retry setting (bits[5:3]). [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w number of delay time units (see register 0xfe3e). the iin_oc_fast_fault_response command instructs the device on the actions to take due to an input fast overcurrent fault condition. the device notifies the host and sets the none_of_the_above bit in status_byte register, the mfr_specific bit in status_word register, and the iin_oc_fast_fault bit in status_mfr_specific register. table 168. register 0xfe37iin_oc_fast_fault_response bits bit name r/w description [7:6] response r/w determines the device response to a fast input overcurrent fault condition. bit 7 bit 6 response 0 0 operate in current limiting mode, maintaining the output current at iout_oc_fault_limit. 0 1 operate in current limiting mode, maintaining the output current at iout_oc_fault_limit. if v out falls below the iout_oc_lv_fault_limit, respond as programmed by the retry setting (bits[5:3]). 1 0 continue operation in current limiting mode for the delay time (bits[2:0]). if the device is still in current limiting mode , respond as programmed by the retry setting (bits[5:3]). 1 1 shut down, disable the output, and re spond as programmed by the retry setting (bits[5:3]). data sheet adp1055 rev. a | page 103 of 140 bits bit name r/w description [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w number of delay time units (see register 0xfe3e). the ishare_fault_response command instructs the device on the actions to take due to a current sharing fault condition. the device notifies the host and sets the none_of_the_above bit in status_byte register, the iout bit in status_word register, and the ishare_fault bit in status_mfr_specific register. table 169. register 0xfe38ishare_fault_response bits bit name r/w description [7:6] response r/w determines the device res ponse to a current shar ing fault condition. bit 7 bit 6 response 0 0 operate in current limiting mode, maintaining the output current at iout_oc_fault_limit. 0 1 operate in current limiting mode, maintaining the output current at iout_oc_fault_limit. if v out falls below the iout_oc_lv_fault_limit, respond as programmed by the retry setting (bits[5:3]). 1 0 continue operation in current limiting mode for the delay time (bits[2:0]). if the device is still in current limiting mode , respond as programmed by the retry setting (bits[5:3]). 1 1 shut down, disable the output, and re spond as programmed by the retry setting (bits[5:3]). [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w number of delay time units (see register 0xfe3e). adp1055 data sheet rev. a | page 104 of 140 the gpio1_fault_response command instructs the device on the actions to take due to a gpio1 fault condition. the device notifie s the host and sets the none_of_the_above bit in status_byte register, the mfr_specific bit in status_word register, and the gpio1_fault bit in status_mfr_specific register. table 170. register 0xfe39gpio1_fault_response bits bit name r/w description [7:6] response r/w determines the device response to a gpio1 fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the delay time (bits[2:0]). if the fault persists, retry the number of times specified by bits[5:3]. 1 0 shut down, disable the output, and re spond as programmed in the retry setting (bits[5:3]). 1 1 disable the output while th e fault is present. operation resumes and the output is enabled when the faul t condition no longer exists. [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay time r/w number of delay time units (see register 0xfe3e). the gpio2_fault_response command instructs the device on the actions to take due to a gpio2 fault condition. the device notifie s the host and sets the none_of_the_above bit in status_byte register, the mfr_specific bit in status_word register, and the gpio2_fault bit in status_mfr_specific register. table 171. register 0xfe3agpio2_fault_response bits bit name r/w description [7:6] response r/w determines the device response to a gpio2 fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the delay time (bits[2:0]). if the fault persists, retry the number of times specified by bits[5:3]. 1 0 shut down, disable the output, and re spond as programmed in the retry setting (bits[5:3]). 1 1 disable the output while th e fault is present. operation resumes and the output is enabled when the faul t condition no longer exists. [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay time r/w number of delay time units (see register 0xfe3e). data sheet adp1055 rev. a | page 105 of 140 the gpio3_fault_response command instructs the device on the actions to take due to a gpio3 fault condition. the device notifie s the host and sets the none_of_the_above bit in status_byte register, the mfr_specific bit in status_word register, and the gpio3_fault bit in status_mfr_specific register. table 172. register 0xfe3bgpio3_fault_response bits bit name r/w description [7:6] response r/w determines the device response to a gpio3 fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the delay time (bits[2:0]). if the fault persists, retry the number of times specified by bits[5:3]. 1 0 shut down, disable the output, and re spond as programmed in the retry setting (bits[5:3]). 1 1 disable the output while th e fault is present. operation resumes and the output is enabled when the faul t condition no longer exists. [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay time r/w number of delay time units (see register 0xfe3e). the gpio4_fault_response command instructs the device on the actions to take due to a gpio4 fault condition. the device notifie s the host and sets the none_of_the_above bit in status_byte register, the mfr_specific bit in status_word register, and the gpio4_fault bit in status_mfr_specific register. table 173. register 0xfe3cgpio4_fault_response bits bit name r/w description [7:6] response r/w determines the device response to a gpio4 fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the delay time (bits[2:0]). if the fault persists, retry the number of times specified by bits[5:3]. 1 0 shut down, disable the output, and re spond as programmed in the retry setting (bits[5:3]). 1 1 disable the output while th e fault is present. operation resumes and the output is enabled when the faul t condition no longer exists. [5:3] retry setting r/w number of retry attempts following a fault condition. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay time r/w number of delay time units (see register 0xfe3e). adp1055 data sheet rev. a | page 106 of 140 register 0xfe3d masks pwm disabling when a fault condition causes the device to disable the output and wait for the fault to cl ear (response[7:6] = 11). note that this masking register applies only when the adp1055 is servicing a fault condition that has the fault response programmed to bits[7:6] = 11. table 174. register 0xfe3dpwm_fault_mask bits bit name r/w description [7:6] reserved r reserved. 5 mask sr2 r/w 0 = sr2 disabled on fault; 1 = sr2 ignores fault. 4 mask sr1 r/w 0 = sr1 disabled on fault; 1 = sr1 ignores fault. 3 mask outd r/w 0 = outd disabled on fault; 1 = outd ignores fault. 2 mask outc r/w 0 = outc disabled on fault; 1 = outc ignores fault. 1 mask outb r/w 0 = outb disabled on fault; 1 = outb ignores fault. 0 mask outa r/w 0 = outa disabled on fault; 1 = outa ignores fault. table 175. register 0xfe3edelay_time_unit bits bit name r/w description 7 current fault delay time unit r/w 0 = ms. 1 = s. [6:4] current fault delay time multiplier r/w bit 6 bit 5 bit 4 multiplier 0 0 0 1 0 0 1 4 0 1 0 16 0 1 1 64 1 0 0 128 1 0 1 256 1 1 0 512 1 1 1 1024 3 voltage/other fault delay time unit r/w 0 = ms. 1 = s. [2:0] voltage/other fault delay time multiplier r/w bit 2 bit 1 bit 0 multiplier 0 0 0 1 0 0 1 4 0 1 0 16 0 1 1 64 1 0 0 128 1 0 1 256 1 1 0 512 1 1 1 1024 table 176. register 0xfe3fwdt_setting bits bit name r/w description [7:2] reserved r reserved. [1:0] watchdog timeout bit 1 bit 0 timeout 0 0 disable 0 1 1 sec 1 0 5 sec 1 1 10 sec data sheet adp1055 rev. a | page 107 of 140 table 177. register 0xfe40gpio_setting bits bit name r/w description 7 gpio4 polarity r/w 0 = active high; 1 = active low 6 gpio4 direction r/w 0 = input; 1 = output 5 gpio3 polarity r/w 0 = active high; 1 = active low 4 gpio3 direction r/w 0 = input; 1 = output 3 gpio2 polarity r/w 0 = active high; 1 = active low 2 gpio2 direction r/w 0 = input; 1 = output 1 gpio1 polarity r/w 0 = active high; 1 = active low 0 gpio1 direction r/w 0 = input; 1 = output table 178. register 0xfe41gpio1_2_karnaugh_map bits bit name r/w description [7:4] gpio2 logic function r/w 0x0 = gnd 0x1 = pgood1 and pgood2 0x2 = pgood1 and ~pgood2 0x3 = pgood1 0x4 = ~pgood1 and pgood2 0x5 = pgood2 0x6 = pgood1 xor pgood2 0x7 = pgood1 or pgood2 0x8 = pgood1 nor pgood2 0x9 = pgood1 xnor pgood2 0xa = ~pgood2 0xb = pgood1 or ~pgood2 0xc = ~pgood1 0xd = ~pgood1 or pgood2 0xe = pgood1 nand pgood2 0xf = vdd [3:0] gpio1 logic function r/w 0x0 = gnd 0x1 = pgood1 and pgood2 0x2 = pgood1 and ~pgood2 0x3 = pgood1 0x4 = ~pgood1 and pgood2 0x5 = pgood2 0x6 = pgood1 xor pgood2 0x7 = pgood1 or pgood2 0x8 = pgood1 nor pgood2 0x9 = pgood1 xnor pgood2 0xa = ~pgood2 0xb = pgood1 or ~pgood2 0xc = ~pgood1 0xd = ~pgood1 or pgood2 0xe = pgood1 nand pgood2 0xf = vdd adp1055 data sheet rev. a | page 108 of 140 table 179. register 0xfe42gpio3_4_karnaugh_map bits bit name r/w description [7:4] gpio4 logic function r/w 0x0 = gnd 0x1 = pgood1 and pgood2 0x2 = pgood1 and ~pgood2 0x3 = pgood1 0x4 = ~pgood1 and pgood2 0x5 = pgood2 0x6 = pgood1 xor pgood2 0x7 = pgood1 or pgood2 0x8 = pgood1 nor pgood2 0x9 = pgood1 xnor pgood2 0xa = ~pgood2 0xb = pgood1 or ~pgood2 0xc = ~pgood1 0xd = ~pgood1 or pgood2 0xe = pgood1 nand pgood2 0xf = vdd [3:0] gpio3 logic function r/w 0x0 = gnd 0x1 = pgood1 and pgood2 0x2 = pgood1 and ~pgood2 0x3 = pgood1 0x4 = ~pgood1 and pgood2 0x5 = pgood2 0x6 = pgood1 xor pgood2 0x7 = pgood1 or pgood2 0x8 = pgood1 nor pgood2 0x9 = pgood1 xnor pgood2 0xa = ~pgood2 0xb = pgood1 or ~pgood2 0xc = ~pgood1 0xd = ~pgood1 or pgood2 0xe = pgood1 nand pgood2 0xf = vdd table 180. register 0xfe43pgood_fault_deb bits bit name r/w description [7:6] pgood2_off_deb r/w bit 7 bit 6 debounce (ms) 0 0 0 0 1 150 + 10 1 0 350 + 10 1 1 550 + 10 [5:4] pgood2_on_deb r/w bit 5 bit 4 debounce (ms) 0 0 0 0 1 150 + 10 1 0 350 + 10 1 1 550 + 10 [3:2] pgood1_off_deb r/w bit 3 bit 2 debounce (ms) 0 0 0 0 1 150 + 10 1 0 350 + 10 1 1 550 + 10 data sheet adp1055 rev. a | page 109 of 140 bits bit name r/w description [1:0] pgood1_on_deb r/w bit 1 bit 0 debounce (ms) 0 0 0 0 1 150 + 10 1 0 350 + 10 1 1 550 + 10 table 181. register 0xfe44pgood1_fault_select bits bit name r/w description 15 ton_max_fault r/w 1 = this flag, if asserted, sets the pgood1 flag (bit 6 of status_unknown) 14 iout_uc_fault r/w 1 = this flag, if asserted, sets the pgood1 flag (bit 6 of status_unknown) 13 pout_op_fault r/w 1 = this flag, if asserted, sets the pgood1 flag (bit 6 of status_unknown) 12 iin_oc_fault r/w 1 = this flag, if asserted, se ts the pgood1 flag (bit 6 of status_unknown) 11 vin_ov_fault r/w 1 = this flag, if asserted, sets the pgood1 flag (bit 6 of status_unknown) 10 vout_uv_fault r/w 1 = this flag, if asserted, sets the pgood1 flag (bit 6 of status_unknown) 9 vout_ov_fault r/w 1 = this flag, if asserted, sets the pgood1 flag (bit 6 of status_unknown) 8 iout_oc_fault r/w 1 = this flag, if asserted, sets the pgood1 flag (bit 6 of status_unknown) 7 vin_uv_fault r/w 1 = this flag, if asserted, sets the pgood1 flag (bit 6 of status_unknown) 6 iin_oc_fast_fault r/w 1 = this flag, if asserted, sets the pgood1 flag (bit 6 of status_unknown) 5 iout_oc_fast_fault r/w 1 = this flag, if asserted , sets the pgood1 flag (bit 6 of status_unknown) 4 vout_ov_fast r/w 1 = this flag, if asserted, sets the pgood1 flag (bit 6 of status_unknown) 3 soft_start_ramp r/w 1 = this flag, if asserted, sets the pgood1 flag (bit 6 of status_unknown) 2 ot_fault r/w 1 = this flag, if asserted, se ts the pgood1 flag (bit 6 of status_unknown) 1 sr_off r/w 1 = this flag, if asserted, sets the pgood1 flag (bit 6 of status_unknown) 0 off r/w 1 = this flag, if asserted, sets the pgood1 flag (bit 6 of status_unknown) table 182. register 0xfe45pgood2_fault_select bits bit name r/w description 15 vout (status_word[15]) r/w 1 = this flag, if asserted, sets the pgood2 flag (bit 7 of status_unknown) 14 iout/pout (status_word[14]) r/w 1 = this flag, if asse rted, sets the pgood2 flag (bit 7 of status_unknown) 13 input (status_word[13]) r/w 1 = this flag, if assert ed, sets the pgood2 flag (bit 7 of status_unknown) 12 temperature (status_word[2]) r/w 1 = this flag, if asserted, sets th e pgood2 flag (bit 7 of status_unknown) 11 gpio2/gpio4 r/w 1 = this flag, if asserted, se ts the pgood2 flag (bit 7 of status_unknown) 10 gpio1/gpio3 r/w 1 = this flag, if asserted, se ts the pgood2 flag (bit 7 of status_unknown) 9 toff_max_warn r/w 1 = this flag, if asserted, sets the pgood2 flag (bit 7 of status_unknown) 8 iout_uc_fast_fault r/w 1 = this flag, if asserted , sets the pgood2 flag (bit 7 of status_unknown) 7 constant current r/w 1 = this flag, if asserted , sets the pgood2 flag (bit 7 of status_unknown) 6 iin_oc_fast_fault r/w 1 = this flag, if asserted, sets the pgood2 flag (bit 7 of status_unknown) 5 iout_oc_fast_fault r/w 1 = this flag, if asserted , sets the pgood2 flag (bit 7 of status_unknown) 4 vout_ov_fast r/w 1 = this flag, if asserted, sets the pgood2 flag (bit 7 of status_unknown) 3 soft_start_ramp r/w 1 = this flag, if asserted, sets the pgood2 flag (bit 7 of status_unknown) 2 sync_unlock r/w 1 = this flag, if asserted, se ts the pgood2 flag (bit 7 of status_unknown) 1 maximum black box record reached r/w 1 = this flag, if asserted, sets th e pgood2 flag (bit 7 of status_unknown) 0 soft start filter r/w 1 = this flag, if asserted , sets the pgood2 flag (bit 7 of status_unknown) table 183. register 0xfe46soft_start_blanking bits bit name r/w description 15 vout_ov_fault r/w 1 = this flag is ignored during soft start 14 gpio3/gpio4 snubber r/w 1 = the gpio3/gpio4 sn ubber outputs are disabled during soft start 13 ton_max_fault r/w 1 = this flag is ignored during soft start 12 vin_ov_fault r/w 1 = this flag is ignored during soft start 11 vin_uv_fault r/w 1 = this flag is ignored during soft start adp1055 data sheet rev. a | page 110 of 140 bits bit name r/w description 10 iin_oc_fault r/w 1 = this flag is ignored during soft start 9 iout_oc_fault r/w 1 = this flag is ignored during soft start 8 iout_uc_fault and iout_uc_fast_fault r/w 1 = this flag is ignored during soft start 7 pout_op_fault r/w 1 = this flag is ignored during soft start 6 iin_oc_fast_fault r/w 1 = this flag is ignored during soft start 5 iout_oc_fast_fault r/w 1 = this flag is ignored during soft start 4 vout_ov_fast r/w 1 = this flag is ignored during soft start 3 iout_oc_lv_fault r/w 1 = this flag is ignored during soft start 2 gpio1/gpio3 r/w 1 = this flag is ignored during soft start 1 gpio2/gpio4 r/w 1 = this flag is ignored during soft start 0 ot_fault r/w 1 = this flag is ignored during soft start table 184. register 0xfe47soft_stop_blanking bits bit name r/w description 15 vout_ov_fault r/w 1 = this flag is ignored during soft stop 14 gpio3/gpio4 snubber r/w 1 = the gpio3/gpio4 sn ubber outputs are disabled during soft stop 13 toff_max_warn r/w 1 = this flag is ignored during soft stop 12 vin_ov_fault r/w 1 = this flag is ignored during soft stop 11 vin_uv_fault r/w 1 = this flag is ignored during soft stop 10 iin_oc_fault r/w 1 = this flag is ignored during soft stop 9 iout_oc_fault r/w 1 = this flag is ignored during soft stop 8 iout_uc_fault and iout_uc_fast_fault r/w 1 = this flag is ignored during soft stop 7 pout_op_fault r/w 1 = this flag is ignored during soft stop 6 iin_oc_fast_fault r/w 1 = this flag is ignored during soft stop 5 iout_oc_fast_fault r/w 1 = this flag is ignored during soft stop 4 vout_ov_fast r/w 1 = this flag is ignored during soft stop 3 iout_oc_lv_fault r/w 1 = this flag is ignored during soft stop 2 gpio1/gpio3 r/w 1 = this flag is ignored during soft stop 1 gpio2/gpio4 r/w 1 = this flag is ignored during soft stop 0 ot_fault r/w 1 = this flag is ignored during soft stop table 185. register 0xfe48blackbox_setting bits bit name r/w description [7:3] reserved r reserved. [2] maximum record number r/w sets the maximum record number at which the black box recording feature is disabled. 0 = 150,000. recommended when operating at <85c. 1 = 16,000. recommended when operating at 125c. [1:0] recording options r/w sets black box recording options before shutting down the power supply. the minimum time for the black box to write all the status registers in to the eeprom is approximately 1.1 ms. when black box writing is enabled for the save on every re try shutdown cycle, the minimum retry delay time must be greater than the time to write to the eeprom (1.1 ms). bit 1 bit 0 options 0 0 no recording. 0 1 record only telemetry just before the final shutdown. 1 0 record telemetry of final shutdown and all retry attempts. 1 1 record telemetry of final shutdown, all retry attempts, and normal unit-off per the ctrl pin and the operation command. data sheet adp1055 rev. a | page 111 of 140 table 186. register 0xfe49pwm_disable_setting bits bit name r/w description [7:6] reserved r reserved. 5 sr2 disable r/w setting this bit disables the sr2 output. 4 sr1 disable r/w setting this bit disables the sr1 output. 3 outd disable r/w setting this bit disables the outd output. 2 outc disable r/w setting this bit disables the outc output. 1 outb disable r/w setting this bit disables the outb output. 0 outa disable r/w setting this bit disables the outa output. table 187. register 0xfe4afilter_transition (req uires use of the go bit in register 0xfe00) bits bit name r/w description 7 overshoot protection r/w 0 = disable setpoint reference tracking. 1 = enable setpoint reference tracking (see the integrator windup and output voltage regulation loss (overshoot protection) section). 6 overshoot speed r/w 0 = if v out is out of regulation for 96 out of 128 switching cycles, the reference moves to the last known value of v out (9-bit precision) and tries to return to re gulation at a controlled rate given by the vout_transition_rate command. 1 = if v out is out of regulation for 48 out of 64 switching cycles, v ref tracks v out (9-bit precision). double update rate affects this register. [5:3] hf adc configuration r/w 000 = autocorrection loop disabled. 001 = autocorrection loop bandwidth set to approximately 9 hz. 010 = autocorrection loop bandwidth set to approximately 19 hz. 011 = autocorrection loop bandwidth set to approximately 37 hz. 100 = autocorrection loop bandwidth set to approximately 75 hz. 101 = autocorrection loop bandwidth set to approximately 150 hz. 110 = autocorrection loop bandwidth set to approximately 300 hz. 111 = autocorrection loop bandwidth set to approximately 600 hz. 2 enable soft transition r/w enables soft transition between filter settings to minimize output transients. all four parameters of each filter are linearly transitioned to the new value. [1:0] transition speed r/w the filter changes in 32 steps, with one step applied at the interval specified by these bits. bit 1 bit 0 speed 0 0 32 t sw (total transition time = 32 32 t sw = 1024 t sw ) 0 1 8 t sw (total transition time = 8 32 = 256 t sw ) 1 0 2 t sw (total = 64 t sw ) 1 1 1 t sw (total = 32 t sw ) table 188. register 0xfe4bdeep_llm_setting bits bit name r/w description [7:5] deep llm thresholds r/w these bits set the load current limit on the cs2 adc below which sr1 and sr2 enter deep light load mode. the averaging time, debounce, and hy steresis are programmed in register 0xfe4b. sr outputs are always off in pulse skip mode. bit 7 bit 6 bit 5 thresholds (lsbs) 0 0 0 0 0 0 1 4 0 1 0 8 0 1 1 12 1 0 0 16 1 0 1 20 1 1 0 24 1 1 1 28 adp1055 data sheet rev. a | page 112 of 140 bits bit name r/w description [4:3] deep light load mode averaging speed r/w sets the averaging speed and reso lution used for the deep light load mode thresholds. faster speed corresponds to lower resolution, and therefore to smaller accuracy of the threshold. bit 4 bit 3 speed (s) 0 0 37.5 (six bits) 0 1 82 (seven bits) 1 0 163 (eight bits) 1 1 327 (nine bits) [2:1] deep light load mode hysteresis r/w sets the amount of hysteresis applied to the d eep light load mode thresholds. the size of the lsb is affected by the speed and resolution select ed in bits[4:3]. for example, if the adc range of 30 mv is used with 8-bit resolution, the lsb size is 30 mv/2 8 = 117.187 v. bit 2 bit 1 lsbs 0 0 3 0 1 8 1 0 12 1 1 16 0 fast phase-in r/w 0 = sr transition speed is always the value pr ogrammed during all transitions, as set by register 0xfe5f[7:4]. 1 = the sr transition speed is the value prog rammed in register 0xfe5f[7:4] for the first transition process (whenever that occurs after pson according to the settings), but for every subsequent transition, the sr outputs transi tion at the fastest speed, that is, 5 ns/t sw . table 189. register 0xfe4cdeep_llm_disable_setting bits bit name r/w description 7 sr phase-in enable r/w 0 = disable sr phase-in. 1 = enable sr phase-in. 6 outd disable r/w setting this bit means that outd is disabled if the load current drops below the deep light load threshold. 5 outc disable r/w setting this bit means that outc is disabled if the load current drops below the deep light load threshold. 4 outb disable r/w setting this bit means that outb is disabled if the load current drops below the deep light load threshold. 3 outa disable r/w setting this bit means that outa is disabled if the load current drops below the deep light load threshold. 2 sr2 disable r/w setting this bit means that sr2 are disabled if the load current drops below the deep light load threshold. 1 srs enable during soft stop r/w setting this bit means that sr2 are disabled if the load current drops below the deep light load threshold. 0 srs enable during soft stop r/w setting this bit reenables the srs during soft stop to facilitate discharging the load. the recommended setting is 1. table 190. register 0xfe4dovp_fault_config bits bit name r/w description 7 vdd/vcore ov fault ignore r/w 0 = vdd ov and vcore ov flags are not ignored 1 = vdd ov and vcore ov flags are ignored 6 vdd/vcore ov restart r/w 0 = do not downlo ad eeprom again following a fault shutdown 1 = download eeprom following a fault shutdown 5 vdd/vcore ov debounce r/w 0 = 2 s + 1 s debounce 1 = 500 s + 10 s debounce 4 vdd uv debounce r/w 0 = no debounce 1 = 120 ns debounce data sheet adp1055 rev. a | page 113 of 140 bits bit name r/w description [3:2] vout_ov sampling r/w bit 3 bit 2 sampling 0 0 one sample sets the vout _ov flag (80 s sampling period) 0 1 two consecutive samples that read a value greater than the one set in vout_ov_fault_limit set the vout_o v flag (160 s sampling period) 1 0 three consecutive samples that read a value greater than the one set in vout_ov_fault_limit set the vout_o v flag (240 s sampling period) 1 1 four consecutive samples that read a value greater than the one set in vout_ov_fault_limit set the vout_o v flag (320 s sampling period) [1:0] reserved reserved table 191. register 0xfe4ecs1_setting bits bit name r/w description 7 reserved r reserved. [6:4] cs1 fast ocp blanking r/w set the cs1 fast ocp blanking time to 0 ns, 40 ns, 80 ns, 120 ns, 200 ns, 400 ns, 600 ns, or 800 ns. 3 cs1 fast ocp bypass r/w setting this bit means that the gp io1 pin is used for cs1 fast ocp instead of the cs1 pin. [2:0] cs1 fast ocp timeout r/w set the number of consecutive switching cycles with a cs1 ocp condition before the iin_oc_fast_fault flag is set: 1, 4, 16, 128, 256, 384, 512, or 1024. table 192. register 0xfe4fcs2_setting bits bit name r/w description 7 cc turbo mode r/w reduces the cs2 average time from 328 s to 41 s for cc mode. [6:4] cs2 fast ocp timeout r/w sets the number of consecutive switching cycles with a cs2 ocp condition before the iout_oc_fast_fault flag is set: 1, 4, 16, 128, 256, 384, 512, or 1024. 3 peak constant current mode r/w when this bit is set, cs2 fast ocp cycle-by-cycle pr otection on outa to outd is disabled. the cs2 fast ocp timeout is still active. 2 average constant current disable r/w 0 = average constant current mode is enabled/disabled, as defined by pmbus. threshold = iout_oc_fault_limit. ilim = iout_oc_fault_limit (100 + percentage), where percentage and polarity are defined in register 0xfe5d[3:0]. the current fault response is pmbus compliant. 1 = average constant current mode is always on (not pmbus compliant). threshold = ilim = iout_oc_fault_limit (100 percentage), where percentage and polarity are defined in register 0xfe5d[3:0]. current fault response defaults to these setti ngs (response bits[7:6]). 00 = ignore fault. 01 = ignore fault. 10 = ignore fault. 11 = shut down, disable the output, and respond as programmed in retry setting (bits[5:3]). [1:0] cs2 range r/w sets the cs2 adc range. bit 1 bit 0 adc range (mv) 0 0 30 (low-side sensing) 0 1 60 (low-side sensing) 1 0 480 (high-side sensing) 1 1 reserved adp1055 data sheet rev. a | page 114 of 140 table 193. register 0xfe50pulse_skip_and_shutdown bits bit name r/w description [7:6] addition ps on time after end of soft stop ramp r/w to allow any negative current to dissipate, pwm o utputs such as the sr outputs are kept active after the soft stop ramp-down. bit 7 bit 6 lsbs 0 0 no additional on time at the end of soft stop. all pwm outputs are shut off immediately at end of ramp. the sr pwm outputs continue to increase their modulation limit and completely turn on for the entire switching cycle after the maximum limit is reached. 0 1 2 ms of extra on time. 1 0 4 ms of extra on time. 1 1 8 ms of extra on time. 5 instant sr transition r/w 1 = sr outputs move from llm to normal mode instantly. 0 = sr outputs transition from one mode to anot her (llm to ccm or ccm to llm) at the phase-in speed (recommended). 4 pulse killer mode r/w register 0xfe50[0] kills all pwm outputs that are modulated. however, this bit kills all pwm outputs whether modulated or not (useful for fbps topology where ther e are two fixed duty cycle pwm outputs). 1 = kill all pwm outputs during pulse skip. 0 = do not kill all pwm outputs during pulse skip. 3 end-of-cycle shutdown r/w 0 = all pwm outputs ar e disabled immediately on a shutdown condition. 1 = all pwm outputs are disabled at the end of the switching cycle on a shutdown condition. 2 soft stop pulse skipping enable r/w if set, allow pulse skipping during soft stop (reg ardless of value of bit 1). however, sr1 and sr2 never pulse skip during soft stop. 1 pulse skipping enable r/w 0 = disable. 1 = enable. 0 pulse skipping zero pwm r/w 0 = pulse skipping drives all modulated pwm outputs to 0 v. 1 = sets all modulated edges to t = 0. table 194. register 0xfe51soft_start_setting bits bit name r/w description 7 soft stop enable for current faults r/w 0 = disable soft stop on a current fault. 1 = enable soft stop on a current fault. 6 soft stop enable for other faults r/w 0 = disable soft stop on a voltage fault. 1 = enable soft stop on a voltage and other fault. [5:3] sr phase-in speed up factor during soft stop r/w during the soft stop process, these bits increa se the sr edge transitioning speed that is specified by register 0xfe5f[7:4]. the speed-up factor is 2 x where x is this 3-bit number. the maximum speed of the sr edge is 40 ns per t sw . for example, if register 0xfe5f specifies 5 ns per 4 t sw , setting these three bits to 2 increases the sr speed to 5 ns per t sw (5 ns/4t sw 2 2 ). setting these bits to 3 increases the sr speed to 10 ns per t sw (5 ns/4t sw 2 3 ). setting these bits to 7 increases the sr speed to 40 ns per t sw (the maximum rate). a smaller value means slower sr transitioning. 2 force soft start filter r/w 1 = soft start filter is used rega rdless of whether the low temperature filter is active or not. 1 disable light load filter during soft start r/w 0 = allow switching to dcm filter during soft start. 1 = never switch to dcm filter during soft start. 0 soft start from precharge r/w setting this bit to 1 enables the soft start fr om precharge function. when this function is enabled, the soft start ramp starts from the la st known value of the voltage detected on vs. data sheet adp1055 rev. a | page 115 of 140 table 195. register 0xfe52sr_delay bits bit name r/w description [7:6] sr blanking r/w these bits add blanking to the reverse current co mparator from the falling edges of the sr llm edges. adding dead time to the sr edges effectively gives additional blanking. when the sr outputs are disabled upon a negative going zero crossing transition, they remain disabled for a period of 327 s to 754 s to ensure that the comparator is not falsely triggered. bit 7 bit 6 blanking (ns) 0 0 40 0 1 80 1 0 120 1 1 160 [5:0] sr driver delay r/w these bits specify the 6-bi t representation of the sr delay in steps of 5 ns. 000000 = 0 ns. 000001 = 5 ns. 000010 = 10 ns. 111111 = 63 5 ns = 315 ns. table 196. register 0xfe53modulation_limit bits bit name r/w description 7 full bridge mode r/w enable this bit when operating in full bridge mode. it affects the modulation high limit. [6:0] modulation limits r/w this value sets the minimum/maximum modulation limits relative to the nominal edge value. the resolution depends on the switching frequency range. switching frequency range (khz) resolution corresponding to lsb 48.8 to 97.7 register 0xfe53[6:0] 32 5 ns 97.7 to 195.3 register 0xfe53[6:0] 16 5 ns 195.3 to 390.6 register 0xfe53[6:0] 8 5 ns 390.6 to 781 register 0xfe53[6:0] 4 5 ns f sw > 781 register 0xfe53[6:0] 2 5 ns table 197. register 0xfe55sync (requires use of the go bit in register 0xfe00) bits bit name r/w description 7 reserved r reserved. 6 pll disable r/w 0 = enable sync function. 1 = disable sync function. [5:2] reserved r reserved. 1 jitter enable r/w 1 = enable jitter on clock (to randomize frequency components). 0 5 ns resolution enable r/w 0 = t sw varies in multiples of 10 ns (50% point is sy nchronized with 5 ns; see the external frequency synchronization section). 1 = t sw varies in multiples of 5 ns. table 198. register 0xfe56duty_bal_edgesel bits bit name r/w description [7:4] positive integration of pwm outputs r/w 1 = selects the pwm outputs to be an ded together for positive integration bit 7 = outa bit 6 = outb bit 5 = outc bit 4 = outd [3:0] negative integration of pwm outputs r/w 1 = selects the pwm outputs to be an ded together for negative integration bit 3 = outa bit 2 = outb bit 1 = outc bit 0 = outd adp1055 data sheet rev. a | page 116 of 140 table 199. register 0xfe57double_upd_rate (requi res use of the go bit in register 0xfe00) bits bit name r/w description 7 enable duty balance r/w 0 = disable. 1 = enable. 6 enable ocp duty equalization r/w 1 = enable ocp duty equalization. when ocp o ccurs, shut down any outx that is high and generate an equalizing ocp to balance the co mplementary output. refer to register 0xfe56 for the selection of pwm outputs. [5:4] duty balance averaging time r/w these bits control how rapidly the misbalance information is used to correct for imbalance. bit 5 bit 4 time 0 0 normal value: cycle-by-cycle integral is divided by 8 and applied to outx. 0 1 2 faster: cycle-by-cycle integral is divided by 4 and applied to outx. 1 0 4 faster: cycle-by-cycle integral is divided by 2 and applied to outx. 1 1 8 faster: no averaging; cycle-by-cycle integral is applied on the next cycle to outx. 3 reserved r/w set to 0 for proper operation. [2:1] duty balance and vs balance limit r/w to balance outa and outb, time is added to or subtracted from outa and outb and added to or subtracted from outc and outd, as in vs bala nce. these bits set the maximum balance value. bit 2 bit 1 limit (ns) 0 0 160 0 1 80 1 0 40 1 1 20 0 enable double update rate r/w 0 = disable. 1 = enable. the vin_scale_monitor command sets the gain (k vin ) by which the input sensed voltage at the dut (v in_dut ) is scaled to generate the reading for the read_vin command. read_vin = v in_dut k vin , where k vin = y 2 n . table 200. register 0xfe58vin_scale_monitor bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). the iin_cal_gain command sets the ratio of the voltage at the input current sense pins to the sensed current (in ohms). table 201. register 0xfe59iin_cal_gain bits bit name r/w description [15:11] exponent-n r/w twos complement n-exponen t used in linear data format (x = y 2 n ). [10:0] mantissa-y r/w twos complement y-mantissa used in linear data format (x = y 2 n ). the tsns_setting command is the temperature sensor current select. table 202. register 0xfe5atsns_setting bits bit name r/w description 7 enable reverse diode r/w 1 = enable external reverse temperature sensor [6:5] resolution r/w 11 = 11 bit 10 = 12 bit 01 = 13 bit 00 = 14 bit 4 reserved r/w set this bit to 0 for proper operation. 3 temperature sense level shift disable r/w 0 = enable internal diode level shifter during external t j sense. this setting is recommended for a single-ended (pn) diode connected between jtd and agnd. 1 = disable internal diode level shifter during external t j sense. this setting is recommended for differential sensing. [2:0] temperature sense current select r/w set these bits to 0x04 fo r proper operation (10 a). data sheet adp1055 rev. a | page 117 of 140 table 203. register 0xfe5bauto_go_cmd bits bit name r/w description [7:2] reserved r reserved. 1 frequency auto-go enable r/w 0 = go_cmd, bit 2 (register 0xfe00) is requ ired to latch the programmed frequency in frequency_switch into the internal loop frequency. 1 = write to frequency_switch is automaticall y latched into the internal loop switching frequency. 0 v ref auto-go enable r/w 0 = go_cmd, bit 0 (register 0xfe00) is required to latch the programmed reference voltage in vout_command into the internal loop frequency. 1 = write to any commands affecting the reference voltage is automatically latched into the internal loop reference voltage. commands that affect the reference volt age include vout_command, vout_mode, vout_max, vout_trim, vout_cal_offset, vout_scale_loop, and vout_droop. table 204. register 0xfe5cdiode_emulation bits bit name r/w description [7:5] sr debounce r/w these bits delay the onset of llm or ccm when the light load mode or deep light load mode threshold is crossed. the device transitions from ccm to llm based on the debounce time specified using these bits and the light load mode threshold. the same is true when the device transitions from llm to ccm and is al so valid for deep light load mode. for example, if the device is in ccm and the lo ad current step places the device in llm, the device physically enters llm, that is, the sr outp uts start phasing after the debounce time set by these bits. the same debounce time delays the entry to dcm. entering deep light load mode is possible only if the adp1055 is already in dcm (that is, the device is already below the dcm thresh old) and sr transitioning is finished. bit 7 bit 6 bit 5 debounce time (t sw ) 0 0 0 0 0 0 1 64 0 1 0 128 0 1 1 256 1 0 0 512 1 0 1 768 1 1 0 1152 1 1 1 2048 [4:2] reserved r reserved. 1 diode emulation mode r/w 0 = disable diode emulation mode (sr llm and deep llm are active if the thresholds are correctly set). 1 = enable diode emulation mode (sr llm setting is disabled. only deep llm is active if the threshold is correctly set). once the sr outputs are disabled upon a negative going zero crossing transition, they are disabled for a period of 327 s to 754 s to ensure that the comparator is not falsely triggered. 0 sr toggle rate in diode emulation mode r/w 0 = sr outputs toggle once in one t sw . 1 = sr outputs toggle twice in one t sw (recommended setting). table 205. register 0xfe5dcs2_const_cur_mode bits bit name r/w description [7:6] reserved r reserved. [5:4] slew rate during cc mode (turbo mode only) r/w 00 = nominal slew rate of (8 1.18) v/sec setting 00 provides 2x nominal at vs pins in cc turbo mode 01 = 16 10 = 24 11 = 32 3 cc mode thresholds polarity r/ w 0 = positive (% above ocp limit) 1 = negative (% below ocp limit) adp1055 data sheet rev. a | page 118 of 140 [2:0] cc mode thresholds r/w percentage above or below ocp limit (iout_oc_fault_limit) 00 = 0% 001 = 3.125% 010 = 6.25% 011 = 12.5% 100 = 25% 101 = 50% 11x = 100% the nl_err_gain_factor register applies nonlinear gain. bits[7:6] apply nonlinear gain to the 1% to 2% range, where the total adc range is 5% of 1 v, that is, 50 mv. bits[5:4] apply nonlinear gain to the 2% to 3.2% range, where the total adc range is 5% of 1 v, that is, 50 mv. bits[3:2] apply nonlinear gain to the 3.2% to 3.9% range, where the total adc range is 5% of 1 v, that is, 5 0 mv. bits[1:0] apply nonlinear gain to the 3.9% and greater range, where the total adc range is 5% of 1 v, that is, 50 mv. table 206. register 0xfe5enl_err_gain_factor (re quires use of the go bit in register 0xfe00) bits bit name r/w description [7:6] nonlinear gain, 1% to 2% range r/w bit 7 bit 6 gain 0 0 1 gain 0 1 2 gain or 1.25 (see register 0xfe29[0]) 1 0 4 gain or 1.5 (see register 0xfe29[0]) 1 1 8 gain or 2 (see register 0xfe29[0]) [5:4] nonlinear gain, 2% to 3.2% range r/w bit 5 bit 4 gain 0 0 1 gain 0 1 2 gain or 1.25 (see register 0xfe29[0]) 1 0 4 gain or 1.5 (see register 0xfe29[0]) 1 1 8 gain or 2 (see register 0xfe29[0]) [3:2] nonlinear gain, 3.2% to 3.9% range r/w bit 3 bit 2 gain 0 0 1 gain 0 1 2 gain or 1.25 (see register 0xfe29[0]) 1 0 4 gain or 1.5 (see register 0xfe29[0]) 1 1 8 gain or 2 (see register 0xfe29[0]) [1:0] nonlinear gain, 3.9% or greater range r/w bit 1 bit 0 gain 0 0 1 gain 0 1 2 gain or 1.25 (see register 0xfe29[0]) 1 0 4 gain or 1.5 (see register 0xfe29[0]) 1 1 8 gain or 2 (see register 0xfe29[0]) data sheet adp1055 rev. a | page 119 of 140 table 207. register 0xfe5fsr_setting bits bit name r/w description [7:4] sr phase-in speed r/w sr edges move by 5 ns every 1/2/4/8/16 /32/64/128/256/384/51 2/640/768/832/960/1024 (total of 16). sr outputs are always phased in during soft start, so ft stop, and all mode transitions; for example, if sr outputs enter pulse skip or are disabled, they turn on again at the phase-in speed selected by these bits. bit 7 bit 6 bit 5 bit 4 multiplier 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 0 0 1 1 8 0 1 0 0 16 0 1 0 1 32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 384 1 0 1 0 512 1 0 1 1 640 1 1 0 0 768 1 1 0 1 832 1 1 1 0 960 1 1 1 1 1024 [3:1] sr llm threshold r/w these bits set the load current limit on the cs2 adc below which sr1 and sr2 enter the light load mode (sr on during forward conduction only). averaging time, debounce, and hysteresis are the same values set in register 0xfe4b. bit 3 bit 2 bit 1 thresholds (lsbs) 0 0 0 0 0 0 1 4 0 1 0 8 0 1 1 12 1 0 0 16 1 0 1 20 1 1 0 24 1 1 1 28 0 blank sr during soft start r/w 1 = blank sr during soft start. table 208. register 0xfe60nominal_temp_pole bits bit name r/w description [7:0] add_pz r/w additional pole/zero setting. a value of 0 disables add_pz. the analog frequency (in rad/sec) is located at w = ln(reg_val/256)/t sw , where t sw is the switching period and reg_val is the contents of register 0xfe60 and register 0xfe61 in decimal format. table 209. register 0xfe61low_temp_pole bits bit name r/w description [7:0] add_pz r/w additional pole/zero setting. a value of 0 disables add_pz. the analog pole frequency in rad/sec is located at w = ln(0xfe61[7:0]/256)/t sw , where t sw is the switching period. adp1055 data sheet rev. a | page 120 of 140 table 210. register 0xfe62low_temp_setting bits bit name r/w description 7 add_pz configuration r/w 0 = add_pz is configured as a digital pole. 1 = add_pz is configured as a digital zero. [6:4] low temperature threshold r/w if non-zero, the filter switches from the nmf (normal mode filter) to the ss filter (soft start filter) in steps of 4c. 000 = regular filter operation independent of temp erature unless the sensing point (configured in bits[1:0]) is set to gpio2 (the filter then changes based on the gpio2 pin). 001 = below ?14c, the soft start filter is used for regulation instead of the normal mode filter. 010 = below ?10c, the soft start filter is used for regulation instead of the normal mode filter. 011 = below ?6c, the soft start filter is used for regulation instead of the normal mode filter. 100 = below ?2c, the soft start filter is used for regulation instead of the normal mode filter. 101 = below +2c, the soft start filter is used for regulation instead of the normal mode filter. 110 = below +6c, the soft start filter is used for regulation instead of the normal mode filter. 111 = below +10c, the soft start filter is used for regulation instead of the normal mode filter. [3:2] low temperature hysteresis r/w each bit is 5c of hysteresis. 00 = 5c. 01 = 10c. 10 = 15c. 11 = 20c. [1:0] low temperature sensing point r/w 00 = reserved. 01 = external fwd temperature sensing. 10 = external rev temperature sensing. 11 = rising edge of gpio2. table 211. register 0xfe63gpio3_4_snubber_on_time bits bit name r/w description [7:0] snubber on time r/w maximum on time of gpio3/gpio4 (if sr/outc/ outd goes high, then the gpio3/gpio4 output goes low/high) in units of 20 ns 0x00 = 0 ns 0x01 = 20 ns 0xfe = 5.08 s 0xff = on until srx goes high or outc or outd goes low table 212. register 0xfe64gpio3_4_snubber_delay bits bit name r/w description [7:6] gpio4 snubber enable r/w 00 = disable active snubber on gpio3/gpio4. 01 = only gpio3 is active snubber. gpio3 goes high after the snubber delay time in register 0xfe64[5:0]. 10 = only gpio4 is active snubber. gpio4 goes high after the snubber delay time in register 0xfe64[5:0]. 11 = gpio3 and gpio4 are active snubber outputs. gp io3 is the inverse of sr1 or outc; gpio4 is the inverse of sr2 or outc, depending on register 0xfe65[7]. [5:0] snubber delay r/w dead time delay from fall of sr to rise of gpio3/gp io4, in units of 5 ns, regardless of the polarity of gpio3/gpio4. 0x00 = 0 ns. 0x01 = 5 ns. 0x3f = 315 ns. data sheet adp1055 rev. a | page 121 of 140 table 213. register 0xfe65vout_droop_setting bits bit name r/w description 7 snubber selection r/w 0 = falling edge of srx is used to activate the snubber. 1 = falling edge of outc or outd is used to activate the snubber. [6:3] reserved r reserved. 2 disable vout_ transition_rate r/w 1 = disable. the voltage reference immediat ely jumps to the value set by vout_command. 0 = enable. the output voltage changes from one value to another as programmed by the vout_transition_rate command. [1:0] vout_droop sampling rate r/w for the purposes of vout_droop, iout is sampled at the following intervals: 00 = 7 bits = 82 s. 01 = 8 bits = 164 s. 10 = 9 bits = 327 s. 11 = 10 bits = 655 s. table 214. register 0xfe66nc_burst_mode (requi res use of the go bit in register 0xfe00) bits bit name r/w description [7:6] adc threshold r/w burst occurs if the adc error exceeds the specified threshold. 00 = error threshold > |1%| of 1 v (that is, 10 mv) 01 = error threshold > |2%| of 1 v (that is, 20 mv) 10 = error threshold > |3%| of 1 v (that is, 30 mv) 11 = error threshold > |4%| of 1 v (that is, 40 mv) [5:3] number of burst cycles r/w set to 0 for no burst 2 enable burst in llm/dem only r/w 1 = burst in light load mode and di ode emulation mode only (not in ccm) 0 = burst in any mode [1:0] burst magnitude r/w magnitude of burst in percentage of duty cycle that is added to the present duty cycle 00 = 6.25% 01 = 12.5% 10 = 25% 11 = 50% table 215. register 0xfe67hf_adc_config bits bit name r/w description [7:4] hf adc samples r/w these bits specify the number of samples taken by the flash adc for loop regulation. the number of samples ranges from 1 (bits[7:4] = 0000) to 16 (bits[7:4] = 1111). following are suggested values depending on the frequency range and whet her double update rate is enabled. frequency range (khz) double update rate enabled do uble update rate disabled f sw 250 1111 (16 samples) 1111 (16 samples) 250 < f sw 300 0111 (8 samples) 1111 (16 samples) 300 < f sw 724.638 0011 (4 samples) 1111 (16 samples) 724.638 < f sw 1000 0001 (2 samples) 0111 (8 samples) [3:0] reserved r/w set these bits to 000 for proper operation. table 216. register 0xfe80vs_trim bits bit name r/w description 7 gain polarity r/w 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] gain trim r/w these bits set the amount of gain trim that is a pplied to the vs adc reading. this register trims the voltage at the vs pins for external resistor tolerances. the vs trim must be performed before the load ovp and load uvp trims are performed. the total range for these bits is 6.25%. the lsb = (6.25%)/128. adp1055 data sheet rev. a | page 122 of 140 table 217. register 0xfe81vff_gain_trim bits bit name r/w description 7 gain polarity r/w 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] gain trim r/w these bits set the gain trim for the vff adc. total range is 12.5% with 128 steps in the positive direction and 127 steps in the negative direction, and the lsb = 12.5%/128. table 218. register 0xfe82cs1_gain_trim bits bit name r/w description 7 gain polarity r/w 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] gain trim r/w these bits set the gain trim for the primary side curr ent gain. total range is 12.5% with 128 steps in the positive direction and 127 steps in the negative direction, and the lsb = 12.5%/128. table 219. register 0xfe86tsns_extfwd_gain_trim bits bit name r/w description [7:0] gain trim r/w gain trim in twos complement added to scaling factor (977 for 10-bit resolution set) for external forward diode temperature measurement. for example, register 0xfe5a[6:5] = 00 corresponds to an increase in gain by 1/489% register 0xfe86 = 0x01 corresponds to an increase in gain by 1/977% register 0xfe86 = 0x02 corresponds to an increase in gain by 2/977% table 220. register 0xfe87tsns_extfwd_offset_trim bits bit name r/w description [7:0] offset trim r/w offset trim added to the acquisition result of the forward diode temperature measurement; 1 lsb corresponds to 0.0156c, in twos complement format. maximum correction is 2c. table 221. register 0xfe88tsns_extrev_gain_trim bits bit name r/w description [7:0] gain trim r/w gain trim in twos complement added to scaling factor (977 for 10-bit resolution set) for external reverse diode temperature measurement. for example, register 0xfe88 = 0x01 corresponds to an increase in gain by 1/977% register 0xfe88 = 0x02 corresponds to an increase in gain by 2/977% table 222. register 0xfe89tsns_extrev_offset_trim bits bit name r/w description [7:0] offset trim r/w offset trim added to the acquisition result of the reverse diode temperature measurement; 1 lsb corresponds to 0.0156c, in twos complement format. maximum correction is 2c. table 223. register 0xfe8cfault_vout bits bit name r/w description [7:0] fault_vout r unlatched fault conditions af ter debounce (see status_vout for latched version) table 224. register 0xfe8dfault_iout bits bit name r/w description [7:0] fault_iout r unlatched fault conditions af ter debounce (see status_iout for latched version) table 225. register 0xfe8efault_input bits bit name r/w description [7:0] fault_input r unlatched fault conditions afte r debounce (see status_input for latched version) data sheet adp1055 rev. a | page 123 of 140 table 226. register 0xfe8ffault_temperature bits bit name r/w description [7:0] fault_temperature r unlatched fault conditions afte r debounce (see status_temperature for latched version) table 227. register 0xfe90fault_cml bits bit name r/w description [7:0] fault_cml r unlatched fault conditions af ter debounce (see status_cml for latched version) table 228. register 0xfe91fault_other bits bit name r/w description [7:0] fault_other r unlatched fault conditions after debounce (see status_other for latched version) table 229. register 0xfe92fault_mfr_specific bits bit name r/w description [7:0] fault_mfr_specific r unlatched fault conditions af ter debounce (see status_mfr_specific for latched version) table 230. register 0xfe93fault_unknown bits bit name r/w description [15:0] fault_unknown r unlatched fault conditions af ter debounce (see status_unknown for latched version) table 231. register 0xfe94status_unknown bits bit name r/w description 15 eeprom unlocked r/w the eeprom is unlocked. 14 adaptive dead time r/w adaptive dead time threshold has been crossed. 13 soft start filter r/w the soft start filter is in use. 12 soft start ramp or soft stop ramp r/w the reference is being ramped up (s oft start) or ramped down (soft stop). 11 modulation limit r/w modulation is at its minimum or maximum limit. 10 volt-second and duty balance limit r/w volt-second balance or duty bala nce at is the maximum/minimum limit. 9 light load mode r/w the devi ce is in light load mode. 8 constant current r/w power supply is operating in cons tant current mode (constant current mode is enabled). 7 pgood2 fault r/w pgood2 fault. at leas t one of the flags listed in regist er 0xfe45 has been set (see table 182). 6 pgood1 fault r/w pgood1 fault. at leas t one of the flags listed in regist er 0xfe44 has been set (see table 181). 5 sync unlock r/w sync mode is enabled, b ut unit not locked to sync input frequency. 4 sr off r/w synchronous rectifiers sr1 and sr2 are disabled. this flag is set when one of the following cases is true: sr1 and sr2 are disabled by the user; th e load current has fallen below the threshold in register 0xfe4b[7:5]; a fault has been set th at was configured to disable the synchronous rectifiers; or sr outputs are blanked during so ft start and during a pulse skip condition. 3 address warning r/w i 2 c/pmbus address warning. add resistor value out-of-range. 2 vcore ov r/w 2.5 v vcore is above limit. action is set to immediate shutdown. 1 vdd ov r/w vdd is above limit. the i 2 c interface stays functional, but a unit power-off/power-on sequence is required to restart the power supply. the re sponse to a vdd overvoltage is programmable in register 0xfe4d[6]. 0 vdd uv r/w vdd is below limit. the response to a vdd undervoltage immediate shutdown. adp1055 data sheet rev. a | page 124 of 140 table 232. register 0xfe95first_fault_id bits bit name r/w description [7:0] first-fault id (in hex) r 0x00 = no fault 0x01 = vout_ov 0x02 = vout_ov_fast 0x03 = vout_uv 0x04 = iout_oc_lv 0x05 = vin_ov 0x06 = vin_uv 0x07 = ot 0x08 = ton_max 0x09 = pout_op 0x0a = gpio1 0x0b = gpio2 0x0c = gpio3 0x0d = gpio4 0x0e = iout_oc 0x0f = iout_oc_fast 0x10 = iout_uc 0x11 = iout_uc_fast 0x12 = iin_oc 0x13 = iin_oc_fast 0x14 = ishare table 233. register 0xfe96vff_value bits bit name r/w description [15:0] vff value r this register contains the feedforward informatio n. this value has 12 bits of resolution from bit 13 to bit 2. table 234. register 0xfe97vs_value bits bit name r/w description [15:0] vs value (output voltage) r this register contains the output voltage informat ion. this value has 12 bits of resolution from bit 13 to bit 2. table 235. register 0xfe98cs1_value bits bit name r/w description [15:0] cs1 value (input current) r this register contains the input current informatio n. this value has 12 bits of resolution from bit 13 to bit 2. table 236. register 0xfe99cs2_value bits bit name r/w description [15:0] cs2 value (output current) r this register contains the 12-bit output current information. this value is the voltage drop across the sense resistor. to obtain the current value, divide the value of this register by the sense resistor value. the cs2 pins have a full-s cale input range of 30 mv, 60 mv, or 480 mv (set in register 0xfe4f[1:0]). when the cs2 input range is set to 30 mv, the lsb step size is 7.32 v. for example, at a 15 mv input signal on cs2, the value in this register is 15 mv/7.32 v = 1000 0000 0000. table 237. register 0xfe9apout_value bits bit name r/w description [15:0] cs2 vs value (output power) r this register contains the 16-bit output power in formation. this value is the product of the remote output voltage value (vs) and the output current reading (cs2). data sheet adp1055 rev. a | page 125 of 140 table 238. register 0xfe9breserved bits bit name r/w description [15:0] reserved r reserved. table 239. register 0xfe9ctsns_extfwd_value bits bit name r/w description [15:7] integer r twos complement integer in the range of ?256 to +255 [6:0] decimal r decimal component of the temperature reading table 240. register 0xfe9dtsns_extrev_value bits bit name r/w description [15:7] integer r twos complement integer in the range of ?256 to +255 [6:0] decimal r decimal component of the temperature reading table 241. register 0xfe9fmodulation_value bits bit name r/w description [7:0] modulation value r this register contains the 8-bit modulation informatio n. it outputs the amount of modulation from 0% to 100% that is being placed on the modulating edges. table 242. register 0xfea0ishare_value bits bit name r/w description [7:0] share bus value r this register contains the 8-bit share bus voltage inform ation. if the power supply is the master, this register outputs 0. table 243. register 0xfea3add_adc_value bits bit name r/w description [7:0] add adc value r this register contains the address information. this value has eight bits of resolution. lsb = 1.6/2 8 = 6.25 mv. at 1 v input, the value in this regist er is 160 (0xa0). it is used in conjunction with register 0xd0[5:4]. adp1055 data sheet rev. a | page 126 of 140 supported switching frequencies table 244 lists switching frequencies supported by the adp1055 . for information about setting the switching frequency, see the frequency_switch section. for entries with the same exponent and mantissa values, the entry with the lower period value is vali d. table 244. supported switching frequencies period (ns) frequency (khz) exponent mantissa 20,470 48.85197851 ?4 782 20,460 48.87585533 ?4 782 20,430 48.94762604 ?4 783 20,400 49.01960784 ?4 784 20,380 49.06771344 ?4 785 20,350 49.14004914 ?4 786 20,330 49.18839154 ?4 787 20,300 49.26108374 ?4 788 20,270 49.33399112 ?4 789 20,250 49.38271605 ?4 790 20,220 49.45598417 ?4 791 20,200 49.5049505 ?4 792 20,170 49.57858205 ?4 793 20,150 49.62779156 ?4 794 20,120 49.70178926 ?4 795 20,100 49.75124378 ?4 796 20,070 49.82561036 ?4 797 20,050 49.87531172 ?4 798 20,020 49.95004995 ?4 799 20,000 50 ?4 800 19,970 50.07511267 ?4 801 19,950 50.12531328 ?4 802 19,920 50.20080321 ?4 803 19,900 50.25125628 ?4 804 19,870 50.32712632 ?4 805 19,850 50.37783375 ?4 806 19,820 50.45408678 ?4 807 19,800 50.50505051 ?4 808 19,770 50.58168943 ?4 809 19,750 50.63291139 ?4 810 19,720 50.70993915 ?4 811 19,700 50.76142132 ?4 812 19,680 50.81300813 ?4 813 19,650 50.89058524 ?4 814 19,630 50.94243505 ?4 815 19,600 51.02040816 ?4 816 19,580 51.07252298 ?4 817 19,550 51.15089514 ?4 818 19,530 51.20327701 ?4 819 19,510 51.25576627 ?4 820 19,480 51.33470226 ?4 821 19,460 51.38746146 ?4 822 19,440 51.44032922 ?4 823 19,410 51.51983514 ?4 824 19,390 51.57297576 ?4 825 19,370 51.62622612 ?4 826 19,340 51.70630817 ?4 827 period (ns) frequency (khz) exponent mantissa 19,320 51.75983437 ?4 828 19,300 51.8134715 ?4 829 19,270 51.89413596 ?4 830 19,250 51.94805195 ?4 831 19,230 52.00208008 ?4 832 19,200 52.08333333 ?4 833 19,180 52.13764338 ?4 834 19,160 52.19206681 ?4 835 19,130 52.27391532 ?4 836 19,110 52.32862376 ?4 837 19,090 52.38344683 ?4 838 19,070 52.4383849 ?4 839 19,040 52.5210084 ?4 840 19,020 52.57623554 ?4 841 19,000 52.63157895 ?4 842 18,970 52.71481286 ?4 843 18,950 52.77044855 ?4 844 18,930 52.8262018 ?4 845 18,910 52.88207298 ?4 846 18,890 52.93806247 ?4 847 18,860 53.02226935 ?4 848 18,840 53.07855626 ?4 849 18,820 53.13496281 ?4 850 18,800 53.19148936 ?4 851 18,770 53.27650506 ?4 852 18,750 53.33333333 ?4 853 18,730 53.39028297 ?4 854 18,710 53.44735436 ?4 855 18,690 53.50454789 ?4 856 18,660 53.59056806 ?4 857 18,640 53.64806867 ?4 858 18,620 53.7056928 ?4 859 18,600 53.76344086 ?4 860 18,580 53.82131324 ?4 861 18,560 53.87931034 ?4 862 18,530 53.96654074 ?4 863 18,510 54.02485143 ?4 864 18,490 54.08328826 ?4 865 18,470 54.14185165 ?4 866 18,450 54.20054201 ?4 867 18,430 54.25935974 ?4 868 18,410 54.31830527 ?4 869 18,390 54.37737901 ?4 870 18,360 54.46623094 ?4 871 18,340 54.52562704 ?4 872 18,320 54.58515284 ?4 873 18,300 54.64480874 ?4 874 data sheet adp1055 rev. a | page 127 of 140 period (ns) frequency (khz) exponent mantissa 18,280 54.70459519 ?4 875 18,260 54.7645126 ?4 876 18,240 54.8245614 ?4 877 18,220 54.88474204 ?4 878 18,200 54.94505495 ?4 879 18,180 55.00550055 ?4 880 18,160 55.0660793 ?4 881 18,140 55.12679162 ?4 882 18,120 55.18763797 ?4 883 18,090 55.27915976 ?4 884 18,070 55.34034311 ?4 885 18,050 55.40166205 ?4 886 18,030 55.46311703 ?4 887 18,010 55.5247085 ?4 888 17,990 55.58643691 ?4 889 17,970 55.64830273 ?4 890 17,950 55.71030641 ?4 891 17,930 55.77244841 ?4 892 17,910 55.8347292 ?4 893 17,890 55.89714925 ?4 894 17,870 55.95970901 ?4 895 17,850 56.02240896 ?4 896 17,830 56.08524958 ?4 897 17,810 56.14823133 ?4 898 17,790 56.21135469 ?4 899 17,770 56.27462015 ?4 900 17,750 56.33802817 ?4 901 17,730 56.40157924 ?4 902 17,710 56.46527386 ?4 903 17,690 56.52911249 ?4 904 17,670 56.59309564 ?4 905 17,660 56.62514156 ?4 906 17,640 56.6893424 ?4 907 17,620 56.75368899 ?4 908 17,600 56.81818182 ?4 909 17,580 56.88282139 ?4 910 17,560 56.9476082 ?4 911 17,540 57.01254276 ?4 912 17,520 57.07762557 ?4 913 17,500 57.14285714 ?4 914 17,480 57.20823799 ?4 915 17,460 57.27376861 ?4 916 17,440 57.33944954 ?4 917 17,420 57.40528129 ?4 918 17,410 57.43825388 ?4 919 17,390 57.50431282 ?4 920 17,370 57.57052389 ?4 921 17,350 57.63688761 ?4 922 17,330 57.7034045 ?4 923 17,310 57.7700751 ?4 924 17,290 57.83689994 ?4 925 17,270 57.90387956 ?4 926 17,250 57.97101449 ?4 928 period (ns) frequency (khz) exponent mantissa 17,240 58.00464037 ?4 928 17,220 58.07200929 ?4 929 17,200 58.13953488 ?4 930 17,180 58.20721769 ?4 931 17,160 58.27505828 ?4 932 17,140 58.34305718 ?4 933 17,130 58.37711617 ?4 934 17,110 58.44535359 ?4 935 17,090 58.51375073 ?4 936 17,070 58.58230814 ?4 937 17,050 58.65102639 ?4 938 17,030 58.71990605 ?4 940 17,020 58.75440658 ?4 940 17,000 58.82352941 ?4 941 16,980 58.89281508 ?4 942 16,960 58.96226415 ?4 943 16,940 59.03187721 ?4 945 16,930 59.06674542 ?4 945 16,910 59.13660556 ?4 946 16,890 59.20663114 ?4 947 16,870 59.27682276 ?4 948 16,850 59.34718101 ?4 950 16,840 59.3824228 ?4 950 16,820 59.4530321 ?4 951 16,800 59.52380952 ?4 952 16,780 59.59475566 ?4 954 16,770 59.63029219 ?4 954 16,750 59.70149254 ?4 955 16,730 59.77286312 ?4 956 16,710 59.84440455 ?4 958 16,700 59.88023952 ?4 958 16,680 59.95203837 ?4 959 16,660 60.0240096 ?4 960 16,640 60.09615385 ?4 962 16,630 60.13229104 ?4 962 16,610 60.20469597 ?4 963 16,590 60.27727547 ?4 964 16,580 60.31363088 ?4 965 16,560 60.38647343 ?4 966 16,540 60.45949214 ?4 967 16,520 60.53268765 ?4 969 16,510 60.56935191 ?4 969 16,490 60.64281383 ?4 970 16,470 60.71645416 ?4 971 16,460 60.75334143 ?4 972 16,440 60.82725061 ?4 973 16,420 60.90133983 ?4 974 16,410 60.93845216 ?4 975 16,390 61.01281269 ?4 976 16,370 61.08735492 ?4 977 16,350 61.16207951 ?4 979 16,340 61.1995104 ?4 979 16,320 61.2745098 ?4 980 adp1055 data sheet rev. a | page 128 of 140 period (ns) frequency (khz) exponent mantissa 16,300 61.34969325 ?4 982 16,290 61.38735421 ?4 982 16,270 61.462815 ?4 983 16,260 61.50061501 ?4 984 16,240 61.57635468 ?4 985 16,220 61.65228113 ?4 986 16,210 61.69031462 ?4 987 16,190 61.76652254 ?4 988 16,170 61.84291899 ?4 989 16,160 61.88118812 ?4 990 16,140 61.95786865 ?4 991 16,120 62.03473945 ?4 993 16,110 62.07324643 ?4 993 16,090 62.15040398 ?4 994 16,080 62.18905473 ?4 995 16,060 62.26650062 ?4 996 16,040 62.34413965 ?4 998 16,030 62.38303182 ?4 998 16,010 62.4609619 ?4 999 16,000 62.5 ?4 1000 15,980 62.57822278 ?4 1001 15,960 62.6566416 ?4 1003 15,950 62.69592476 ?4 1003 15,930 62.77463905 ?4 1004 15,920 62.81407035 ?4 1005 15,900 62.89308176 ?4 1006 15,880 62.97229219 ?4 1008 15,870 63.01197227 ?4 1008 15,850 63.09148265 ?4 1009 15,840 63.13131313 ?4 1010 15,820 63.21112516 ?4 1011 15,810 63.25110689 ?4 1012 15,790 63.33122229 ?4 1013 15,770 63.4115409 ?4 1015 15,760 63.45177665 ?4 1015 15,740 63.53240152 ?4 1017 15,730 63.57279085 ?4 1017 15,710 63.65372374 ?4 1018 15,700 63.69426752 ?4 1019 15,680 63.7755102 ?4 1020 15,670 63.81620932 ?4 1021 15,650 63.89776358 ?4 1022 15,640 63.93861893 ?4 1023 15,620 64.02048656 ?3 512 15,590 64.14368185 ?3 513 15,560 64.26735219 ?3 514 15,530 64.39150032 ?3 515 15,500 64.51612903 ?3 516 15,470 64.64124111 ?3 517 15,440 64.76683938 ?3 518 15,410 64.89292667 ?3 519 15,380 65.01950585 ?3 520 15,350 65.1465798 ?3 521 period (ns) frequency (khz) exponent mantissa 15,320 65.27415144 ?3 522 15,290 65.40222368 ?3 523 15,260 65.53079948 ?3 524 15,230 65.65988181 ?3 525 15,200 65.78947368 ?3 526 15,180 65.87615283 ?3 527 15,150 66.00660066 ?3 528 15,120 66.13756614 ?3 529 15,090 66.26905235 ?3 530 15,060 66.40106242 ?3 531 15,030 66.53359947 ?3 532 15,000 66.66666667 ?3 533 14,980 66.75567423 ?3 534 14,950 66.88963211 ?3 535 14,920 67.02412869 ?3 536 14,890 67.15916723 ?3 537 14,860 67.29475101 ?3 538 14,840 67.38544474 ?3 539 14,810 67.52194463 ?3 540 14,780 67.65899865 ?3 541 14,760 67.75067751 ?3 542 14,730 67.88866259 ?3 543 14,700 68.02721088 ?3 544 14,670 68.16632584 ?3 545 14,650 68.25938567 ?3 546 14,620 68.3994528 ?3 547 14,590 68.54009596 ?3 548 14,570 68.63417982 ?3 549 14,540 68.77579092 ?3 550 14,510 68.91798759 ?3 551 14,490 69.01311249 ?3 552 14,460 69.15629322 ?3 553 14,440 69.25207756 ?3 554 14,410 69.3962526 ?3 555 14,380 69.54102921 ?3 556 14,360 69.63788301 ?3 557 14,330 69.78367062 ?3 558 14,310 69.88120196 ?3 559 14,280 70.0280112 ?3 560 14,260 70.12622721 ?3 561 14,230 70.27406887 ?3 562 14,200 70.42253521 ?3 563 14,180 70.52186178 ?3 564 14,150 70.67137809 ?3 565 14,130 70.77140835 ?3 566 14,100 70.92198582 ?3 567 14,080 71.02272727 ?3 568 14,050 71.17437722 ?3 569 14,030 71.27583749 ?3 570 14,010 71.37758744 ?3 571 13,980 71.53075823 ?3 572 13,960 71.63323782 ?3 573 13,930 71.78750897 ?3 574 data sheet adp1055 rev. a | page 129 of 140 period (ns) frequency (khz) exponent mantissa 13,910 71.8907261 ?3 575 13,880 72.04610951 ?3 576 13,860 72.15007215 ?3 577 13,840 72.25433526 ?3 578 13,810 72.41129616 ?3 579 13,790 72.51631617 ?3 580 13,760 72.6744186 ?3 581 13,740 72.78020378 ?3 582 13,720 72.88629738 ?3 583 13,690 73.04601899 ?3 584 13,670 73.15288954 ?3 585 13,650 73.26007326 ?3 586 13,620 73.42143906 ?3 587 13,600 73.52941176 ?3 588 13,580 73.6377025 ?3 589 13,550 73.80073801 ?3 590 13,530 73.90983001 ?3 591 13,510 74.019245 ?3 592 13,490 74.12898443 ?3 593 13,460 74.29420505 ?3 594 13,440 74.4047619 ?3 595 13,420 74.51564829 ?3 596 13,400 74.62686567 ?3 597 13,370 74.79431563 ?3 598 13,350 74.90636704 ?3 599 13,330 75.01875469 ?3 600 13,310 75.13148009 ?3 601 13,280 75.30120482 ?3 602 13,260 75.4147813 ?3 603 13,240 75.52870091 ?3 604 13,220 75.6429652 ?3 605 13,200 75.75757576 ?3 606 13,170 75.93014427 ?3 607 13,150 76.04562738 ?3 608 13,130 76.1614623 ?3 609 13,110 76.27765065 ?3 610 13,090 76.39419404 ?3 611 13,070 76.51109411 ?3 612 13,050 76.62835249 ?3 613 13,020 76.80491551 ?3 614 13,000 76.92307692 ?3 615 12,980 77.04160247 ?3 616 12,960 77.16049383 ?3 617 12,940 77.2797527 ?3 618 12,920 77.3993808 ?3 619 12,900 77.51937984 ?3 620 12,880 77.63975155 ?3 621 12,860 77.76049767 ?3 622 12,840 77.88161994 ?3 623 12,820 78.00312012 ?3 624 12,800 78.125 ?3 625 12,770 78.30853563 ?3 626 12,750 78.43137255 ?3 627 period (ns) frequency (khz) exponent mantissa 12,730 78.55459544 ?3 628 12,710 78.67820614 ?3 629 12,690 78.80220646 ?3 630 12,670 78.92659826 ?3 631 12,650 79.0513834 ?3 632 12,630 79.17656374 ?3 633 12,610 79.30214116 ?3 634 12,590 79.42811755 ?3 635 12,570 79.55449483 ?3 636 12,550 79.6812749 ?3 637 12,530 79.8084597 ?3 638 12,510 79.93605116 ?3 639 12,500 80 ?3 640 12,480 80.12820513 ?3 641 12,460 80.25682183 ?3 642 12,440 80.38585209 ?3 643 12,420 80.51529791 ?3 644 12,400 80.64516129 ?3 645 12,380 80.77544426 ?3 646 12,360 80.90614887 ?3 647 12,340 81.03727715 ?3 648 12,320 81.16883117 ?3 649 12,300 81.30081301 ?3 650 12,280 81.43322476 ?3 651 12,260 81.56606852 ?3 653 12,250 81.63265306 ?3 653 12,230 81.76614881 ?3 654 12,210 81.9000819 ?3 655 12,190 82.03445447 ?3 656 12,170 82.16926869 ?3 657 12,150 82.30452675 ?3 658 12,130 82.44023083 ?3 660 12,120 82.50825083 ?3 660 12,100 82.6446281 ?3 661 12,080 82.78145695 ?3 662 12,060 82.91873964 ?3 663 12,040 83.05647841 ?3 664 12,030 83.12551953 ?3 665 12,010 83.26394671 ?3 666 11,990 83.4028357 ?3 667 11,970 83.54218881 ?3 668 11,950 83.68200837 ?3 669 11,940 83.7520938 ?3 670 11,920 83.89261745 ?3 671 11,900 84.03361345 ?3 672 11,880 84.17508418 ?3 673 11,860 84.31703204 ?3 675 11,850 84.38818565 ?3 675 11,830 84.53085376 ?3 676 11,810 84.67400508 ?3 677 11,790 84.81764207 ?3 679 11,780 84.88964346 ?3 679 11,760 85.03401361 ?3 680 adp1055 data sheet rev. a | page 130 of 140 period (ns) frequency (khz) exponent mantissa 11,740 85.17887564 ?3 681 11,730 85.2514919 ?3 682 11,710 85.3970965 ?3 683 11,690 85.54319932 ?3 684 11,670 85.68980291 ?3 686 11,660 85.76329331 ?3 686 11,640 85.91065292 ?3 687 11,620 86.05851979 ?3 688 11,610 86.13264427 ?3 689 11,590 86.28127696 ?3 690 11,570 86.43042351 ?3 691 11,560 86.50519031 ?3 692 11,540 86.65511265 ?3 693 11,520 86.80555556 ?3 694 11,510 86.88097307 ?3 695 11,490 87.03220191 ?3 696 11,470 87.18395815 ?3 697 11,460 87.2600349 ?3 698 11,440 87.41258741 ?3 699 11,420 87.56567426 ?3 701 11,410 87.64241893 ?3 701 11,390 87.79631255 ?3 702 11,370 87.95074758 ?3 704 11,360 88.02816901 ?3 704 11,340 88.18342152 ?3 705 11,330 88.26125331 ?3 706 11,310 88.4173298 ?3 707 11,290 88.57395926 ?3 709 11,280 88.65248227 ?3 709 11,260 88.80994671 ?3 710 11,250 88.88888889 ?3 711 11,230 89.04719501 ?3 712 11,220 89.12655971 ?3 713 11,200 89.28571429 ?3 714 11,180 89.44543828 ?3 716 11,170 89.52551477 ?3 716 11,150 89.68609865 ?3 717 11,140 89.76660682 ?3 718 11,120 89.92805755 ?3 719 11,110 90.0090009 ?3 720 11,090 90.17132552 ?3 721 11,080 90.25270758 ?3 722 11,060 90.4159132 ?3 723 11,040 90.57971014 ?3 725 11,030 90.66183137 ?3 725 11,010 90.82652134 ?3 727 11,000 90.90909091 ?3 727 10,980 91.07468124 ?3 729 10,970 91.15770283 ?3 729 10,950 91.32420091 ?3 731 10,940 91.40767824 ?3 731 10,920 91.57509158 ?3 733 10,910 91.65902841 ?3 733 period (ns) frequency (khz) exponent mantissa 10,890 91.82736455 ?3 735 10,880 91.91176471 ?3 735 10,860 92.08103131 ?3 737 10,850 92.16589862 ?3 737 10,840 92.25092251 ?3 738 10,820 92.42144177 ?3 739 10,810 92.50693802 ?3 740 10,790 92.67840593 ?3 741 10,780 92.76437848 ?3 742 10,760 92.93680297 ?3 743 10,750 93.02325581 ?3 744 10,730 93.19664492 ?3 746 10,720 93.28358209 ?3 746 10,700 93.45794393 ?3 748 10,690 93.5453695 ?3 748 10,680 93.6329588 ?3 749 10,660 93.80863039 ?3 750 10,650 93.89671362 ?3 751 10,630 94.07337723 ?3 753 10,620 94.16195857 ?3 753 10,610 94.25070688 ?3 754 10,590 94.42870633 ?3 755 10,580 94.51795841 ?3 756 10,560 94.6969697 ?3 758 10,550 94.78672986 ?3 758 10,540 94.87666034 ?3 759 10,520 95.05703422 ?3 760 10,510 95.14747859 ?3 761 10,490 95.32888465 ?3 763 10,480 95.41984733 ?3 763 10,470 95.51098376 ?3 764 10,450 95.6937799 ?3 766 10,440 95.78544061 ?3 766 10,430 95.87727709 ?3 767 10,410 96.06147935 ?3 768 10,400 96.15384615 ?3 769 10,380 96.33911368 ?3 771 10,370 96.43201543 ?3 771 10,360 96.52509653 ?3 772 10,340 96.71179884 ?3 774 10,330 96.8054211 ?3 774 10,320 96.89922481 ?3 775 10,300 97.08737864 ?3 777 10,290 97.18172983 ?3 777 10,280 97.27626459 ?3 778 10,260 97.46588694 ?3 780 10,250 97.56097561 ?3 780 10,240 97.65625 ?3 781 10,230 97.75171065 ?3 782 10,210 97.94319295 ?3 784 10,200 98.03921569 ?3 784 10,190 98.13542689 ?3 785 10,170 98.32841691 ?3 787 data sheet adp1055 rev. a | page 131 of 140 period (ns) frequency (khz) exponent mantissa 10,160 98.42519685 ?3 787 10,150 98.52216749 ?3 788 10,130 98.71668312 ?3 790 10,120 98.81422925 ?3 791 10,110 98.91196835 ?3 791 10,100 99.00990099 ?3 792 10,080 99.20634921 ?3 794 10,070 99.30486594 ?3 794 10,060 99.40357853 ?3 795 10,050 99.50248756 ?3 796 10,030 99.70089731 ?3 798 10,020 99.8003992 ?3 798 10,010 99.9000999 ?3 799 10,000 100 ?3 800 9980 100.2004008 ?3 802 9970 100.3009027 ?3 802 9960 100.4016064 ?3 803 9950 100.5025126 ?3 804 9930 100.7049345 ?3 806 9920 100.8064516 ?3 806 9910 100.9081736 ?3 807 9900 101.010101 ?3 808 9880 101.2145749 ?3 810 9870 101.3171226 ?3 811 9860 101.4198783 ?3 811 9850 101.5228426 ?3 812 9840 101.6260163 ?3 813 9820 101.8329939 ?3 815 9810 101.9367992 ?3 815 9800 102.0408163 ?3 816 9790 102.145046 ?3 817 9770 102.3541453 ?3 819 9760 102.4590164 ?3 820 9750 102.5641026 ?3 821 9740 102.6694045 ?3 821 9730 102.7749229 ?3 822 9720 102.8806584 ?3 823 9700 103.0927835 ?3 825 9690 103.1991744 ?3 826 9680 103.3057851 ?3 826 9670 103.4126163 ?3 827 9660 103.5196687 ?3 828 9650 103.626943 ?3 829 9630 103.8421599 ?3 831 9620 103.950104 ?3 832 9610 104.0582726 ?3 832 9600 104.1666667 ?3 833 9590 104.2752868 ?3 834 9580 104.3841336 ?3 835 9560 104.6025105 ?3 837 9550 104.7120419 ?3 838 9540 104.8218029 ?3 839 9530 104.9317943 ?3 839 period (ns) frequency (khz) exponent mantissa 9520 105.0420168 ?3 840 9510 105.1524711 ?3 841 9500 105.2631579 ?3 842 9480 105.4852321 ?3 844 9470 105.5966209 ?3 845 9460 105.7082452 ?3 846 9450 105.8201058 ?3 847 9440 105.9322034 ?3 847 9430 106.0445387 ?3 848 9420 106.1571125 ?3 849 9410 106.2699256 ?3 850 9400 106.3829787 ?3 851 9380 106.6098081 ?3 853 9370 106.7235859 ?3 854 9360 106.8376068 ?3 855 9350 106.9518717 ?3 856 9340 107.0663812 ?3 857 9330 107.1811361 ?3 857 9320 107.2961373 ?3 858 9310 107.4113856 ?3 859 9300 107.5268817 ?3 860 9290 107.6426265 ?3 861 9280 107.7586207 ?3 862 9260 107.9913607 ?3 864 9250 108.1081081 ?3 865 9240 108.2251082 ?3 866 9230 108.3423619 ?3 867 9220 108.4598698 ?3 868 9210 108.577633 ?3 869 9200 108.6956522 ?3 870 9190 108.8139282 ?3 871 9180 108.9324619 ?3 871 9170 109.0512541 ?3 872 9160 109.1703057 ?3 873 9150 109.2896175 ?3 874 9140 109.4091904 ?3 875 9130 109.5290252 ?3 876 9120 109.6491228 ?3 877 9110 109.7694841 ?3 878 9100 109.8901099 ?3 879 9090 110.0110011 ?3 880 9080 110.1321586 ?3 881 9070 110.2535832 ?3 882 9060 110.3752759 ?3 883 9040 110.619469 ?3 885 9030 110.7419712 ?3 886 9020 110.864745 ?3 887 9010 110.9877913 ?3 888 9000 111.1111111 ?3 889 8990 111.2347052 ?3 890 8980 111.3585746 ?3 891 8970 111.4827202 ?3 892 8960 111.6071429 ?3 893 adp1055 data sheet rev. a | page 132 of 140 period (ns) frequency (khz) exponent mantissa 8950 111.7318436 ?3 894 8940 111.8568233 ?3 895 8930 111.9820829 ?3 896 8920 112.1076233 ?3 897 8910 112.2334456 ?3 898 8900 112.3595506 ?3 899 8890 112.4859393 ?3 900 8880 112.6126126 ?3 901 8870 112.7395716 ?3 902 8860 112.8668172 ?3 903 8850 112.9943503 ?3 904 8840 113.1221719 ?3 905 8830 113.2502831 ?3 906 8820 113.3786848 ?3 907 8810 113.507378 ?3 908 8800 113.6363636 ?3 909 8790 113.7656428 ?3 910 8780 113.8952164 ?3 911 8770 114.0250855 ?3 912 8760 114.1552511 ?3 913 8750 114.2857143 ?3 914 8740 114.416476 ?3 915 8730 114.5475372 ?3 916 8720 114.6788991 ?3 917 8710 114.8105626 ?3 918 8700 114.9425287 ?3 920 8690 115.0747986 ?3 921 8680 115.2073733 ?3 922 8670 115.3402537 ?3 923 8660 115.4734411 ?3 924 8650 115.6069364 ?3 925 8640 115.7407407 ?3 926 8630 115.8748552 ?3 927 8620 116.0092807 ?3 928 8610 116.1440186 ?3 929 8600 116.2790698 ?3 930 8590 116.4144354 ?3 931 8580 116.5501166 ?3 932 8570 116.6861144 ?3 933 8560 116.8224299 ?3 935 8550 116.9590643 ?3 936 8540 117.0960187 ?3 937 8530 117.2332943 ?3 938 8520 117.370892 ?3 939 8510 117.5088132 ?3 940 8500 117.6470588 ?3 941 8490 117.7856302 ?3 942 8480 117.9245283 ?3 943 8470 118.0637544 ?3 945 8460 118.2033097 ?3 946 8450 118.3431953 ?3 947 8440 118.4834123 ?3 948 8430 118.623962 ?3 949 period (ns) frequency (khz) exponent mantissa 8420 118.7648456 ?3 950 8410 118.9060642 ?3 951 8400 119.047619 ?3 952 8390 119.1895113 ?3 954 8380 119.3317422 ?3 955 8370 119.474313 ?3 956 8360 119.6172249 ?3 957 8350 119.760479 ?3 958 8340 119.9040767 ?3 959 8330 120.0480192 ?3 960 8320 120.1923077 ?3 962 8310 120.3369434 ?3 963 8300 120.4819277 ?3 964 8290 120.6272618 ?3 965 8280 120.7729469 ?3 966 8270 120.9189843 ?3 967 8260 121.0653753 ?3 969 8250 121.2121212 ?3 970 8240 121.3592233 ?3 971 8230 121.5066829 ?3 972 8220 121.6545012 ?3 973 8210 121.8026797 ?3 974 8200 121.9512195 ?3 976 8190 122.1001221 ?3 977 8180 122.2493888 ?3 978 8170 122.3990208 ?3 979 8160 122.5490196 ?3 980 8150 122.6993865 ?3 982 8140 122.8501229 ?3 983 8130 123.00123 ?3 984 8120 123.1527094 ?3 985 8110 123.3045623 ?3 986 8100 123.4567901 ?3 988 8090 123.6093943 ?3 989 8080 123.7623762 ?3 990 8070 123.9157373 ?3 991 8060 124.0694789 ?3 993 8050 124.2236025 ?3 994 8040 124.3781095 ?3 995 8030 124.5330012 ?3 996 8020 124.6882793 ?3 998 8010 124.8439451 ?3 999 8000 125 ?3 1000 7990 125.1564456 ?3 1001 7980 125.3132832 ?3 1003 7970 125.4705144 ?3 1004 7960 125.6281407 ?3 1005 7950 125.7861635 ?3 1006 7940 125.9445844 ?3 1008 7930 126.1034048 ?3 1009 7920 126.2626263 ?3 1010 7910 126.4222503 ?3 1011 7900 126.5822785 ?3 1013 data sheet adp1055 rev. a | page 133 of 140 period (ns) frequency (khz) exponent mantissa 7890 126.7427123 ?3 1014 7880 126.9035533 ?3 1015 7870 127.064803 ?3 1017 7860 127.2264631 ?3 1018 7850 127.388535 ?3 1019 7840 127.5510204 ?3 1020 7830 127.7139208 ?3 1022 7820 127.8772379 ?3 1023 7810 128.0409731 ?2 512 7790 128.3697047 ?2 513 7780 128.5347044 ?2 514 7760 128.8659794 ?2 515 7750 129.0322581 ?2 516 7730 129.3661061 ?2 517 7720 129.5336788 ?2 518 7700 129.8701299 ?2 519 7690 130.0390117 ?2 520 7670 130.3780965 ?2 522 7660 130.5483029 ?2 522 7640 130.8900524 ?2 524 7630 131.061599 ?2 524 7610 131.4060447 ?2 526 7600 131.5789474 ?2 526 7590 131.7523057 ?2 527 7570 132.1003963 ?2 528 7560 132.2751323 ?2 529 7540 132.6259947 ?2 531 7530 132.8021248 ?2 531 7510 133.1557923 ?2 533 7500 133.3333333 ?2 533 7490 133.5113485 ?2 534 7470 133.8688086 ?2 535 7460 134.0482574 ?2 536 7440 134.4086022 ?2 538 7430 134.589502 ?2 538 7420 134.7708895 ?2 539 7400 135.1351351 ?2 541 7390 135.3179973 ?2 541 7380 135.501355 ?2 542 7360 135.8695652 ?2 543 7350 136.0544218 ?2 544 7330 136.425648 ?2 546 7320 136.6120219 ?2 546 7310 136.7989056 ?2 547 7290 137.1742112 ?2 549 7280 137.3626374 ?2 549 7270 137.5515818 ?2 550 7250 137.9310345 ?2 552 7240 138.121547 ?2 552 7230 138.3125864 ?2 553 7220 138.5041551 ?2 554 7200 138.8888889 ?2 556 7190 139.0820584 ?2 556 period (ns) frequency (khz) exponent mantissa 7180 139.275766 ?2 557 7160 139.6648045 ?2 559 7150 139.8601399 ?2 559 7140 140.0560224 ?2 560 7130 140.2524544 ?2 561 7110 140.6469761 ?2 563 7100 140.8450704 ?2 563 7090 141.0437236 ?2 564 7070 141.4427157 ?2 566 7060 141.6430595 ?2 567 7050 141.8439716 ?2 567 7040 142.0454545 ?2 568 7020 142.4501425 ?2 570 7010 142.6533524 ?2 571 7000 142.8571429 ?2 571 6990 143.0615165 ?2 572 6980 143.2664756 ?2 573 6960 143.6781609 ?2 575 6950 143.8848921 ?2 576 6940 144.092219 ?2 576 6930 144.3001443 ?2 577 6920 144.5086705 ?2 578 6900 144.9275362 ?2 580 6890 145.137881 ?2 581 6880 145.3488372 ?2 581 6870 145.5604076 ?2 582 6860 145.7725948 ?2 583 6840 146.1988304 ?2 585 6830 146.4128843 ?2 586 6820 146.627566 ?2 587 6810 146.8428781 ?2 587 6800 147.0588235 ?2 588 6790 147.275405 ?2 589 6770 147.7104874 ?2 591 6760 147.9289941 ?2 592 6750 148.1481481 ?2 593 6740 148.3679525 ?2 593 6730 148.5884101 ?2 594 6720 148.8095238 ?2 595 6710 149.0312966 ?2 596 6700 149.2537313 ?2 597 6680 149.7005988 ?2 599 6670 149.9250375 ?2 600 6660 150.1501502 ?2 601 6650 150.3759398 ?2 602 6640 150.6024096 ?2 602 6630 150.8295626 ?2 603 6620 151.0574018 ?2 604 6610 151.2859304 ?2 605 6600 151.5151515 ?2 606 6580 151.9756839 ?2 608 6570 152.2070015 ?2 609 6560 152.4390244 ?2 610 adp1055 data sheet rev. a | page 134 of 140 period (ns) frequency (khz) exponent mantissa 6550 152.6717557 ?2 611 6540 152.9051988 ?2 612 6530 153.1393568 ?2 613 6520 153.3742331 ?2 613 6510 153.609831 ?2 614 6500 153.8461538 ?2 615 6490 154.0832049 ?2 616 6480 154.3209877 ?2 617 6470 154.5595054 ?2 618 6460 154.7987616 ?2 619 6450 155.0387597 ?2 620 6440 155.2795031 ?2 621 6430 155.5209953 ?2 622 6420 155.7632399 ?2 623 6410 156.0062402 ?2 624 6400 156.25 ?2 625 6380 156.7398119 ?2 627 6370 156.9858713 ?2 628 6360 157.2327044 ?2 629 6350 157.480315 ?2 630 6340 157.7287066 ?2 631 6330 157.9778831 ?2 632 6320 158.2278481 ?2 633 6310 158.4786054 ?2 634 6300 158.7301587 ?2 635 6290 158.9825119 ?2 636 6280 159.2356688 ?2 637 6270 159.4896332 ?2 638 6260 159.7444089 ?2 639 6250 160 ?2 640 6240 160.2564103 ?2 641 6230 160.5136437 ?2 642 6220 160.7717042 ?2 643 6210 161.0305958 ?2 644 6200 161.2903226 ?2 645 6190 161.5508885 ?2 646 6180 161.8122977 ?2 647 6170 162.0745543 ?2 648 6160 162.3376623 ?2 649 6150 162.601626 ?2 650 6140 162.8664495 ?2 651 6130 163.132137 ?2 653 6120 163.3986928 ?2 654 6110 163.6661211 ?2 655 6100 163.9344262 ?2 656 6090 164.2036125 ?2 657 6080 164.4736842 ?2 658 6070 164.7446458 ?2 659 6060 165.0165017 ?2 660 6050 165.2892562 ?2 661 6040 165.5629139 ?2 662 6030 165.8374793 ?2 663 6020 166.1129568 ?2 664 period (ns) frequency (khz) exponent mantissa 6010 166.3893511 ?2 666 6000 166.6666667 ?2 667 5990 166.9449082 ?2 668 5980 167.2240803 ?2 669 5970 167.5041876 ?2 670 5960 167.7852349 ?2 671 5950 168.0672269 ?2 672 5940 168.3501684 ?2 673 5930 168.6340641 ?2 675 5920 168.9189189 ?2 676 5910 169.2047377 ?2 677 5900 169.4915254 ?2 678 5890 169.7792869 ?2 679 5880 170.0680272 ?2 680 5870 170.3577513 ?2 681 5860 170.6484642 ?2 683 5850 170.9401709 ?2 684 5840 171.2328767 ?2 685 5830 171.5265866 ?2 686 5820 171.8213058 ?2 687 5810 172.1170396 ?2 688 5800 172.4137931 ?2 690 5790 172.7115717 ?2 691 5780 173.0103806 ?2 692 5770 173.3102253 ?2 693 5760 173.6111111 ?2 694 5750 173.9130435 ?2 696 5740 174.2160279 ?2 697 5730 174.5200698 ?2 698 5720 174.8251748 ?2 699 5710 175.1313485 ?2 701 5700 175.4385965 ?2 702 5690 175.7469244 ?2 703 5680 176.056338 ?2 704 5670 176.366843 ?2 705 5660 176.6784452 ?2 707 5650 176.9911504 ?2 708 5640 177.3049645 ?2 709 5630 177.6198934 ?2 710 5620 177.9359431 ?2 712 5610 178.2531194 ?2 713 5600 178.5714286 ?2 714 5590 178.8908766 ?2 716 5580 179.2114695 ?2 717 5570 179.5332136 ?2 718 5560 179.8561151 ?2 719 5550 180.1801802 ?2 721 5540 180.5054152 ?2 722 5530 180.8318264 ?2 723 5520 181.1594203 ?2 725 5510 181.4882033 ?2 726 5500 181.8181818 ?2 727 5490 182.1493625 ?2 729 data sheet adp1055 rev. a | page 135 of 140 period (ns) frequency (khz) exponent mantissa 5480 182.4817518 ?2 730 5470 182.8153565 ?2 731 5460 183.1501832 ?2 733 5450 183.4862385 ?2 734 5440 183.8235294 ?2 735 5430 184.1620626 ?2 737 5420 184.501845 ?2 738 5410 184.8428835 ?2 739 5400 185.1851852 ?2 741 5390 185.528757 ?2 742 5380 185.8736059 ?2 743 5370 186.2197393 ?2 745 5360 186.5671642 ?2 746 5350 186.9158879 ?2 748 5340 187.2659176 ?2 749 5330 187.6172608 ?2 750 5320 187.9699248 ?2 752 5310 188.3239171 ?2 753 5300 188.6792453 ?2 755 5290 189.0359168 ?2 756 5280 189.3939394 ?2 758 5270 189.7533207 ?2 759 5260 190.1140684 ?2 760 5250 190.4761905 ?2 762 5240 190.8396947 ?2 763 5230 191.2045889 ?2 765 5220 191.5708812 ?2 766 5210 191.9385797 ?2 768 5200 192.3076923 ?2 769 5190 192.6782274 ?2 771 5180 193.0501931 ?2 772 5170 193.4235977 ?2 774 5160 193.7984496 ?2 775 5150 194.1747573 ?2 777 5140 194.5525292 ?2 778 5130 194.9317739 ?2 780 5120 195.3125 ?2 781 5110 195.6947162 ?2 783 5100 196.0784314 ?2 784 5090 196.4636542 ?2 786 5080 196.8503937 ?2 787 5070 197.2386588 ?2 789 5060 197.6284585 ?2 791 5050 198.019802 ?2 792 5040 198.4126984 ?2 794 5030 198.8071571 ?2 795 5020 199.2031873 ?2 797 5010 199.6007984 ?2 798 5000 200 ?2 800 4990 200.4008016 ?2 802 4980 200.8032129 ?2 803 4970 201.2072435 ?2 805 4960 201.6129032 ?2 806 period (ns) frequency (khz) exponent mantissa 4950 202.020202 ?2 808 4940 202.4291498 ?2 810 4930 202.8397566 ?2 811 4920 203.2520325 ?2 813 4910 203.6659878 ?2 815 4900 204.0816327 ?2 816 4890 204.4989775 ?2 818 4880 204.9180328 ?2 820 4870 205.338809 ?2 821 4860 205.7613169 ?2 823 4850 206.185567 ?2 825 4840 206.6115702 ?2 826 4830 207.0393375 ?2 828 4820 207.4688797 ?2 830 4810 207.9002079 ?2 832 4800 208.3333333 ?2 833 4790 208.7682672 ?2 835 4780 209.2050209 ?2 837 4770 209.6436059 ?2 839 4760 210.0840336 ?2 840 4750 210.5263158 ?2 842 4740 210.9704641 ?2 844 4730 211.4164905 ?2 846 4720 211.8644068 ?2 847 4710 212.3142251 ?2 849 4700 212.7659574 ?2 851 4690 213.2196162 ?2 853 4680 213.6752137 ?2 855 4670 214.1327623 ?2 857 4660 214.5922747 ?2 858 4650 215.0537634 ?2 860 4640 215.5172414 ?2 862 4630 215.9827214 ?2 864 4620 216.4502165 ?2 866 4610 216.9197397 ?2 868 4600 217.3913043 ?2 870 4590 217.8649237 ?2 871 4580 218.3406114 ?2 873 4570 218.8183807 ?2 875 4560 219.2982456 ?2 877 4550 219.7802198 ?2 879 4540 220.2643172 ?2 881 4530 220.7505519 ?2 883 4520 221.2389381 ?2 885 4510 221.72949 ?2 887 4500 222.2222222 ?2 889 4490 222.7171492 ?2 891 4480 223.2142857 ?2 893 4470 223.7136465 ?2 895 4460 224.2152466 ?2 897 4450 224.7191011 ?2 899 4440 225.2252252 ?2 901 4430 225.7336343 ?2 903 adp1055 data sheet rev. a | page 136 of 140 period (ns) frequency (khz) exponent mantissa 4420 226.2443439 ?2 905 4410 226.7573696 ?2 907 4400 227.2727273 ?2 909 4390 227.7904328 ?2 911 4380 228.3105023 ?2 913 4370 228.8329519 ?2 915 4360 229.3577982 ?2 917 4350 229.8850575 ?2 920 4340 230.4147465 ?2 922 4330 230.9468822 ?2 924 4320 231.4814815 ?2 926 4310 232.0185615 ?2 928 4300 232.5581395 ?2 930 4290 233.1002331 ?2 932 4280 233.6448598 ?2 935 4270 234.1920375 ?2 937 4260 234.741784 ?2 939 4250 235.2941176 ?2 941 4240 235.8490566 ?2 943 4230 236.4066194 ?2 946 4220 236.9668246 ?2 948 4210 237.5296912 ?2 950 4200 238.0952381 ?2 952 4190 238.6634845 ?2 955 4180 239.2344498 ?2 957 4170 239.8081535 ?2 959 4160 240.3846154 ?2 962 4150 240.9638554 ?2 964 4140 241.5458937 ?2 966 4130 242.1307506 ?2 969 4120 242.7184466 ?2 971 4110 243.3090024 ?2 973 4100 243.902439 ?2 976 4090 244.4987775 ?2 978 4080 245.0980392 ?2 980 4070 245.7002457 ?2 983 4060 246.3054187 ?2 985 4050 246.9135802 ?2 988 4040 247.5247525 ?2 990 4030 248.1389578 ?2 993 4020 248.7562189 ?2 995 4010 249.3765586 ?2 998 4000 250 ?2 1000 3990 250.6265664 ?2 1003 3980 251.2562814 ?2 1005 3970 251.8891688 ?2 1008 3960 252.5252525 ?2 1010 3950 253.164557 ?2 1013 3940 253.8071066 ?2 1015 3930 254.4529262 ?2 1018 3920 255.1020408 ?2 1020 3910 255.7544757 ?2 1023 3900 256.4102564 ?1 513 period (ns) frequency (khz) exponent mantissa 3890 257.0694087 ?1 514 3880 257.7319588 ?1 515 3870 258.3979328 ?1 517 3860 259.0673575 ?1 518 3850 259.7402597 ?1 519 3840 260.4166667 ?1 521 3830 261.0966057 ?1 522 3820 261.7801047 ?1 524 3810 262.4671916 ?1 525 3800 263.1578947 ?1 526 3790 263.8522427 ?1 528 3780 264.5502646 ?1 529 3770 265.2519894 ?1 531 3760 265.9574468 ?1 532 3750 266.6666667 ?1 533 3740 267.3796791 ?1 535 3730 268.0965147 ?1 536 3720 268.8172043 ?1 538 3710 269.541779 ?1 539 3700 270.2702703 ?1 541 3690 271.00271 ?1 542 3680 271.7391304 ?1 543 3670 272.479564 ?1 545 3660 273.2240437 ?1 546 3650 273.9726027 ?1 548 3640 274.7252747 ?1 549 3630 275.4820937 ?1 551 3620 276.2430939 ?1 552 3610 277.0083102 ?1 554 3600 277.7777778 ?1 556 3590 278.551532 ?1 557 3580 279.3296089 ?1 559 3570 280.1120448 ?1 560 3560 280.8988764 ?1 562 3550 281.6901408 ?1 563 3540 282.4858757 ?1 565 3530 283.286119 ?1 567 3520 284.0909091 ?1 568 3510 284.9002849 ?1 570 3500 285.7142857 ?1 571 3490 286.5329513 ?1 573 3480 287.3563218 ?1 575 3470 288.184438 ?1 576 3460 289.017341 ?1 578 3450 289.8550725 ?1 580 3440 290.6976744 ?1 581 3430 291.5451895 ?1 583 3420 292.3976608 ?1 585 3410 293.255132 ?1 587 3400 294.1176471 ?1 588 3390 294.9852507 ?1 590 3380 295.8579882 ?1 592 3370 296.735905 ?1 593 data sheet adp1055 rev. a | page 137 of 140 period (ns) frequency (khz) exponent mantissa 3360 297.6190476 ?1 595 3350 298.5074627 ?1 597 3340 299.4011976 ?1 599 3330 300.3003003 ?1 601 3320 301.2048193 ?1 602 3310 302.1148036 ?1 604 3300 303.030303 ?1 606 3290 303.9513678 ?1 608 3280 304.8780488 ?1 610 3270 305.8103976 ?1 612 3260 306.7484663 ?1 613 3250 307.6923077 ?1 615 3240 308.6419753 ?1 617 3230 309.5975232 ?1 619 3220 310.5590062 ?1 621 3210 311.5264798 ?1 623 3200 312.5 ?1 625 3190 313.4796238 ?1 627 3180 314.4654088 ?1 629 3170 315.4574132 ?1 631 3160 316.4556962 ?1 633 3150 317.4603175 ?1 635 3140 318.4713376 ?1 637 3130 319.4888179 ?1 639 3120 320.5128205 ?1 641 3110 321.5434084 ?1 643 3100 322.5806452 ?1 645 3090 323.6245955 ?1 647 3080 324.6753247 ?1 649 3070 325.732899 ?1 651 3060 326.7973856 ?1 654 3050 327.8688525 ?1 656 3040 328.9473684 ?1 658 3030 330.0330033 ?1 660 3020 331.1258278 ?1 662 3010 332.2259136 ?1 664 3000 333.3333333 ?1 667 2990 334.4481605 ?1 669 2980 335.5704698 ?1 671 2970 336.7003367 ?1 673 2960 337.8378378 ?1 676 2950 338.9830508 ?1 678 2940 340.1360544 ?1 680 2930 341.2969283 ?1 683 2920 342.4657534 ?1 685 2910 343.6426117 ?1 687 2900 344.8275862 ?1 690 2890 346.0207612 ?1 692 2880 347.2222222 ?1 694 2870 348.4320557 ?1 697 2860 349.6503497 ?1 699 2850 350.877193 ?1 702 2840 352.1126761 ?1 704 period (ns) frequency (khz) exponent mantissa 2830 353.3568905 ?1 707 2820 354.6099291 ?1 709 2810 355.8718861 ?1 712 2800 357.1428571 ?1 714 2790 358.4229391 ?1 717 2780 359.7122302 ?1 719 2770 361.0108303 ?1 722 2760 362.3188406 ?1 725 2750 363.6363636 ?1 727 2740 364.9635036 ?1 730 2730 366.3003663 ?1 733 2720 367.6470588 ?1 735 2710 369.00369 ?1 738 2700 370.3703704 ?1 741 2690 371.7472119 ?1 743 2680 373.1343284 ?1 746 2670 374.5318352 ?1 749 2660 375.9398496 ?1 752 2650 377.3584906 ?1 755 2640 378.7878788 ?1 758 2630 380.2281369 ?1 760 2620 381.6793893 ?1 763 2610 383.1417625 ?1 766 2600 384.6153846 ?1 769 2590 386.1003861 ?1 772 2580 387.5968992 ?1 775 2570 389.1050584 ?1 778 2560 390.625 ?1 781 2550 392.1568627 ?1 784 2540 393.7007874 ?1 787 2530 395.256917 ?1 791 2520 396.8253968 ?1 794 2510 398.4063745 ?1 797 2500 400 ?1 800 2490 401.6064257 ?1 803 2480 403.2258065 ?1 806 2470 404.8582996 ?1 810 2460 406.504065 ?1 813 2450 408.1632653 ?1 816 2440 409.8360656 ?1 820 2430 411.5226337 ?1 823 2420 413.2231405 ?1 826 2410 414.9377593 ?1 830 2400 416.6666667 ?1 833 2390 418.4100418 ?1 837 2380 420.1680672 ?1 840 2370 421.9409283 ?1 844 2360 423.7288136 ?1 847 2350 425.5319149 ?1 851 2340 427.3504274 ?1 855 2330 429.1845494 ?1 858 2320 431.0344828 ?1 862 2310 432.9004329 ?1 866 adp1055 data sheet rev. a | page 138 of 140 period (ns) frequency (khz) exponent mantissa 2300 434.7826087 ?1 870 2290 436.6812227 ?1 873 2280 438.5964912 ?1 877 2270 440.5286344 ?1 881 2260 442.4778761 ?1 885 2250 444.4444444 ?1 889 2240 446.4285714 ?1 893 2230 448.4304933 ?1 897 2220 450.4504505 ?1 901 2210 452.4886878 ?1 905 2200 454.5454545 ?1 909 2190 456.6210046 ?1 913 2180 458.7155963 ?1 917 2170 460.8294931 ?1 922 2160 462.962963 ?1 926 2150 465.1162791 ?1 930 2140 467.2897196 ?1 935 2130 469.4835681 ?1 939 2120 471.6981132 ?1 943 2110 473.9336493 ?1 948 2100 476.1904762 ?1 952 2090 478.4688995 ?1 957 2080 480.7692308 ?1 962 2070 483.0917874 ?1 966 2060 485.4368932 ?1 971 2050 487.804878 ?1 976 2040 490.1960784 ?1 980 2030 492.6108374 ?1 985 2020 495.049505 ?1 990 2010 497.5124378 ?1 995 2000 500 ?1 1000 1990 502.5125628 ?1 1005 1980 505.0505051 ?1 1010 1970 507.6142132 ?1 1015 1960 510.2040816 ?1 1020 1950 512.8205128 0 513 1940 515.4639175 0 515 1930 518.134715 0 518 1920 520.8333333 0 521 1910 523.5602094 0 524 1900 526.3157895 0 526 1890 529.1005291 0 529 1880 531.9148936 0 532 1870 534.7593583 0 535 1860 537.6344086 0 538 1850 540.5405405 0 541 1840 543.4782609 0 543 1830 546.4480874 0 546 1820 549.4505495 0 549 1810 552.4861878 0 552 1800 555.5555556 0 556 1790 558.6592179 0 559 1780 561.7977528 0 562 period (ns) frequency (khz) exponent mantissa 1770 564.9717514 0 565 1760 568.1818182 0 568 1750 571.4285714 0 571 1740 574.7126437 0 575 1730 578.0346821 0 578 1720 581.3953488 0 581 1710 584.7953216 0 585 1700 588.2352941 0 588 1690 591.7159763 0 592 1680 595.2380952 0 595 1670 598.8023952 0 599 1660 602.4096386 0 602 1650 606.0606061 0 606 1640 609.7560976 0 610 1630 613.4969325 0 613 1620 617.2839506 0 617 1610 621.1180124 0 621 1600 625 0 625 1590 628.9308176 0 629 1580 632.9113924 0 633 1570 636.9426752 0 637 1560 641.025641 0 641 1550 645.1612903 0 645 1540 649.3506494 0 649 1530 653.5947712 0 654 1520 657.8947368 0 658 1510 662.2516556 0 662 1500 666.6666667 0 667 1490 671.1409396 0 671 1480 675.6756757 0 676 1470 680.2721088 0 680 1460 684.9315068 0 685 1450 689.6551724 0 690 1440 694.4444444 0 694 1430 699.3006993 0 699 1420 704.2253521 0 704 1410 709.2198582 0 709 1400 714.2857143 0 714 1390 719.4244604 0 719 1380 724.6376812 0 725 1370 729.9270073 0 730 1360 735.2941176 0 735 1350 740.7407407 0 741 1340 746.2686567 0 746 1330 751.8796992 0 752 1320 757.5757576 0 758 1310 763.3587786 0 763 1300 769.2307692 0 769 1290 775.1937984 0 775 1280 781.25 0 781 1270 787.4015748 0 787 1260 793.6507937 0 794 1250 800 0 800 data sheet adp1055 rev. a | page 139 of 140 period (ns) frequency (khz) exponent mantissa 1240 806.4516129 0 806 1230 813.0081301 0 813 1220 819.6721311 0 820 1210 826.446281 0 826 1200 833.3333333 0 833 1190 840.3361345 0 840 1180 847.4576271 0 847 1170 854.7008547 0 855 1160 862.0689655 0 862 1150 869.5652174 0 870 1140 877.1929825 0 877 1130 884.9557522 0 885 1120 892.8571429 0 893 period (ns) frequency (khz) exponent mantissa 1110 900.9009009 0 901 1100 909.0909091 0 909 1090 917.4311927 0 917 1080 925.9259259 0 926 1070 934.5794393 0 935 1060 943.3962264 0 943 1050 952.3809524 0 952 1040 961.5384615 0 962 1030 970.8737864 0 971 1020 980.3921569 0 980 1010 990.0990099 0 990 1000 1000 0 1000 adp1055 data sheet rev. a | page 140 of 140 outline dimensions figure 86. 32-lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp-32-12) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adp1055acpz-rl ?40c to +125c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-12 adp1055acpz-r7 ?40c to +125c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-12 adp1055-evalz adp1055 evaluation board adp1055dc1-evalz adp1055 daughter card ADP-I2C-USB-Z usb to i 2 c adapter 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). 08-16-2010-b 1 0.50 bsc bottom view top view pin 1 indicator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r seating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min * 3.75 3.60 sq 3.55 * compliant to jedec standards mo-220-whhd-5 with the exception of the exposed pad dimension. ?2014C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d12004-0-3/15(a) |
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